subdev/pmu/gm20b.c

28 #include <nvfw/pmu.h>
42 	struct nvkm_pmu *pmu = container_of(falcon, typeof(*pmu), falcon);
52 	ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr,
54 				    &pmu->subdev, msecs_to_jiffies(1000));
129 	struct nvkm_pmu *pmu = priv;
130 	struct nvkm_subdev *subdev = &pmu->subdev;
139 	complete_all(&pmu->wpr_ready);
144 gm20b_pmu_acr_init_wpr(struct nvkm_pmu *pmu)
154 	return nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr,
155 				     gm20b_pmu_acr_init_wpr_callback, pmu, 0);
159 gm20b_pmu_initmsg(struct nvkm_pmu *pmu)
164 	ret = nvkm_falcon_msgq_recv_initmsg(pmu->msgq, &msg, sizeof(msg));
172 	nvkm_falcon_cmdq_init(pmu->hpq, msg.queue_info[0].index,
175 	nvkm_falcon_cmdq_init(pmu->lpq, msg.queue_info[1].index,
178 	nvkm_falcon_msgq_init(pmu->msgq, msg.queue_info[4].index,
181 	return gm20b_pmu_acr_init_wpr(pmu);
185 gm20b_pmu_recv(struct nvkm_pmu *pmu)
187 	if (!pmu->initmsg_received) {
188 		int ret = pmu->func->initmsg(pmu);
190 			nvkm_error(&pmu->subdev, "error parsing init message: %d\n", ret);
194 		pmu->initmsg_received = true;
197 	nvkm_falcon_msgq_recv(pmu->msgq);
201 gm20b_pmu_fini(struct nvkm_pmu *pmu)
205 	flush_work(&pmu->recv.work);
206 	nvkm_falcon_cmdq_fini(pmu->lpq);
207 	nvkm_falcon_cmdq_fini(pmu->hpq);
209 	reinit_completion(&pmu->wpr_ready);
211 	nvkm_falcon_put(&pmu->falcon, &pmu->subdev);
215 gm20b_pmu_init(struct nvkm_pmu *pmu)
217 	struct nvkm_falcon *falcon = &pmu->falcon;
222 	ret = nvkm_falcon_get(&pmu->falcon, &pmu->subdev);
226 	pmu->initmsg_received = false;
245 MODULE_FIRMWARE("nvidia/gm20b/pmu/desc.bin");
246 MODULE_FIRMWARE("nvidia/gm20b/pmu/image.bin");
247 MODULE_FIRMWARE("nvidia/gm20b/pmu/sig.bin");
251 gm20b_pmu_load(struct nvkm_pmu *pmu, int ver, const struct nvkm_pmu_fwif *fwif)
253 	return nvkm_acr_lsfw_load_sig_image_desc(&pmu->subdev, &pmu->falcon,
254 						 NVKM_ACR_LSF_PMU, "pmu/",