| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 992 display_e2e_pipe_params_st *pipes) in dcn20_populate_dml_writeback_from_context() argument
1005 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; in dcn20_populate_dml_writeback_from_context()
1006 pipes[pipe_cnt].dout.num_active_wb++; in dcn20_populate_dml_writeback_from_context()
1007 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; in dcn20_populate_dml_writeback_from_context()
1008 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; in dcn20_populate_dml_writeback_from_context()
1009 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; in dcn20_populate_dml_writeback_from_context()
1010 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; in dcn20_populate_dml_writeback_from_context()
1011 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; in dcn20_populate_dml_writeback_from_context()
1012 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; in dcn20_populate_dml_writeback_from_context()
1013 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; in dcn20_populate_dml_writeback_from_context()
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| H A D | dcn20_fpu.h | 33 display_e2e_pipe_params_st *pipes);
37 display_e2e_pipe_params_st *pipes,
41 display_e2e_pipe_params_st *pipes,
46 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
65 enum dc_validate_mode validate_mode, display_e2e_pipe_params_st *pipes);
77 display_e2e_pipe_params_st *pipes,
80 dc_validate_mode, display_e2e_pipe_params_st *pipes);
87 display_e2e_pipe_params_st *pipes);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 182 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) in dcn30_fpu_populate_dml_writeback_from_context() argument
199 pipes[pipe_cnt].dout.wb_enable = 0; in dcn30_fpu_populate_dml_writeback_from_context()
200 pipes[pipe_cnt].dout.num_active_wb = 0; in dcn30_fpu_populate_dml_writeback_from_context()
206 pipes[pipe_cnt].dout.wb_enable = 1; in dcn30_fpu_populate_dml_writeback_from_context()
207 pipes[pipe_cnt].dout.num_active_wb++; in dcn30_fpu_populate_dml_writeback_from_context()
250 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz, in dcn30_fpu_populate_dml_writeback_from_context()
257 pipes[pipe_cnt].pipe.dest.htotal, in dcn30_fpu_populate_dml_writeback_from_context()
262 pipes[pipe_cnt].dout.wb = dout_wb; in dcn30_fpu_populate_dml_writeback_from_context()
273 display_e2e_pipe_params_st *pipes, in dcn30_fpu_set_mcif_arb_params() argument
282 wb_arb_params->cli_watermark[i] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000; in dcn30_fpu_set_mcif_arb_params()
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| H A D | dcn30_fpu.h | 33 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
37 display_e2e_pipe_params_st *pipes,
45 display_e2e_pipe_params_st *pipes,
65 display_e2e_pipe_params_st *pipes,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 296 display_e2e_pipe_params_st *pipes, in calculate_wm_set_for_vlevel() argument
303 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
305 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
311 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
312 …wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) … in calculate_wm_set_for_vlevel()
313 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
314 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
315 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
316 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 308 display_e2e_pipe_params_st *pipes, in dcn314_populate_dml_pipes_from_context_fpu() argument
319 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, validate_mode); in dcn314_populate_dml_pipes_from_context_fpu()
334 pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; in dcn314_populate_dml_pipes_from_context_fpu()
336 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; in dcn314_populate_dml_pipes_from_context_fpu()
340 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn314_populate_dml_pipes_from_context_fpu()
341 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); in dcn314_populate_dml_pipes_from_context_fpu()
346 pipes[pipe_cnt].pipe.dest.vblank_nom = in dcn314_populate_dml_pipes_from_context_fpu()
347 max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2); in dcn314_populate_dml_pipes_from_context_fpu()
348 …pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblan… in dcn314_populate_dml_pipes_from_context_fpu()
357 … pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled || dc->res_pool->hubbub->riommu_active; in dcn314_populate_dml_pipes_from_context_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 277 display_e2e_pipe_params_st *pipes, in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
293 …dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, DC_VALIDATE_MODE_AND_PROGRAMMIN… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
295 /* for subvp + DRR case, if subvp pipes are still present we support pstate */ in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
322 * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes
326 * @pipes: [in] DML pipe params array
329 * This function must be called AFTER the phantom pipes are added to context
330 * and run through DML (so that the DLG params for the phantom pipes can be
331 * populated), and BEFORE we program the timing for the phantom pipes.
335 display_e2e_pipe_params_st *pipes, in dcn32_helper_populate_phantom_dlg_params() argument
349 pipes[pipe_idx].pipe.dest.vstartup_start = in dcn32_helper_populate_phantom_dlg_params()
[all …]
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| H A D | dcn32_fpu.h | 36 display_e2e_pipe_params_st *pipes,
43 display_e2e_pipe_params_st *pipes,
49 display_e2e_pipe_params_st *pipes,
55 display_e2e_pipe_params_st *pipes,
63 display_e2e_pipe_params_st *pipes,
69 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
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| /linux/drivers/gpu/drm/amd/display/dc/link/accessories/ |
| H A D | link_dp_cts.c | 69 struct pipe_ctx *pipes[MAX_PIPES]; in dp_retrain_link_dp_test() local
85 link_get_master_pipes_with_dpms_on(link, state, &count, pipes); in dp_retrain_link_dp_test()
88 link_set_dpms_off(pipes[i]); in dp_retrain_link_dp_test()
89 pipes[i]->link_config.dp_link_settings = *link_setting; in dp_retrain_link_dp_test()
93 pipes[i]); in dp_retrain_link_dp_test()
96 pipes[i]->stream_res.tg->funcs->disable_crtc(pipes[i]->stream_res.tg); in dp_retrain_link_dp_test()
102 *pipes, &audio_output[0]); in dp_retrain_link_dp_test()
104 pipes[i]->clock_source->funcs->program_pix_clk( in dp_retrain_link_dp_test()
105 pipes[i]->clock_source, in dp_retrain_link_dp_test()
106 &pipes[i]->stream_res.pix_clk_params, in dp_retrain_link_dp_test()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 472 display_e2e_pipe_params_st *pipes, in dcn351_populate_dml_pipes_from_context_fpu() argument
481 dcn31_populate_dml_pipes_from_context(dc, context, pipes, in dcn351_populate_dml_pipes_from_context_fpu()
501 pipes[pipe_cnt].pipe.dest.vtotal = in dcn351_populate_dml_pipes_from_context_fpu()
503 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - in dcn351_populate_dml_pipes_from_context_fpu()
504 pipes[pipe_cnt].pipe.dest.vactive; in dcn351_populate_dml_pipes_from_context_fpu()
507 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn351_populate_dml_pipes_from_context_fpu()
508 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); in dcn351_populate_dml_pipes_from_context_fpu()
513 pipes[pipe_cnt].pipe.dest.vblank_nom = in dcn351_populate_dml_pipes_from_context_fpu()
514 max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2); in dcn351_populate_dml_pipes_from_context_fpu()
515 …pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblan… in dcn351_populate_dml_pipes_from_context_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 439 display_e2e_pipe_params_st *pipes, in dcn35_populate_dml_pipes_from_context_fpu() argument
448 dcn31_populate_dml_pipes_from_context(dc, context, pipes, in dcn35_populate_dml_pipes_from_context_fpu()
468 pipes[pipe_cnt].pipe.dest.vtotal = in dcn35_populate_dml_pipes_from_context_fpu()
470 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - in dcn35_populate_dml_pipes_from_context_fpu()
471 pipes[pipe_cnt].pipe.dest.vactive; in dcn35_populate_dml_pipes_from_context_fpu()
474 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn35_populate_dml_pipes_from_context_fpu()
475 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); in dcn35_populate_dml_pipes_from_context_fpu()
480 pipes[pipe_cnt].pipe.dest.vblank_nom = in dcn35_populate_dml_pipes_from_context_fpu()
481 max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2); in dcn35_populate_dml_pipes_from_context_fpu()
482 …pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblan… in dcn35_populate_dml_pipes_from_context_fpu()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 46 const display_e2e_pipe_params_st *pipes,
54 const display_e2e_pipe_params_st *pipes, in dml_get_voltage_level() argument
60 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
65 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
68 if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0) in dml_get_voltage_level()
82 …attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_…
84 recalculate_params(mode_lib, pipes, num_pipes); \
130 …attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_…
133 recalculate_params(mode_lib, pipes, num_pipes); \
209 const display_e2e_pipe_params_st *pipes, in get_total_immediate_flip_bytes() argument
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| /linux/Documentation/driver-api/ |
| H A D | xillybus.rst | 17 -- Seekable pipes
23 -- Channels, pipes, and the message channel
85 project to another (the number of data pipes needed in each direction and
90 Xillybus presents independent data streams, which resemble pipes or TCP/IP
125 possibly pressing CTRL-C as some stage, even though the xillybus_* pipes have
128 The driver and hardware are designed to behave sensibly as pipes, including:
138 device files are treated like two independent pipes (except for sharing a
144 Xillybus pipes are configured (on the IP core) to be either synchronous or
154 For FPGA to host pipes, asynchronous pipes allow data transfer from the FPGA
156 has been requested by a read() call. On synchronous pipes, only the amount
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 445 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, in dcn31_zero_pipe_dcc_fraction() argument
450 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; in dcn31_zero_pipe_dcc_fraction()
451 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; in dcn31_zero_pipe_dcc_fraction()
484 display_e2e_pipe_params_st *pipes, in dcn31_calculate_wm_and_dlg_fp() argument
506 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
508 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
511 get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn31_calculate_wm_and_dlg_fp()
513 …if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_tim… in dcn31_calculate_wm_and_dlg_fp()
523 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
[all …]
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| /linux/drivers/gpu/drm/arm/display/komeda/ |
| H A D | komeda_event.c | 110 return (a->pipes[0] | a->pipes[1]) & in is_new_frame()
120 u64 evts_mask = evts->global | evts->pipes[0] | evts->pipes[1]; in komeda_print_events()
146 komeda_sprintf(&str, ", pipes[0]: "); in komeda_print_events()
147 evt_str(&str, evts->pipes[0]); in komeda_print_events()
148 komeda_sprintf(&str, ", pipes[1]: "); in komeda_print_events()
149 evt_str(&str, evts->pipes[1]); in komeda_print_events()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.h | 51 display_e2e_pipe_params_st *pipes,
64 display_e2e_pipe_params_st *pipes,
71 display_e2e_pipe_params_st *pipes,
76 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
80 display_e2e_pipe_params_st *pipes,
106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 112 /* merge pipes if necessary */ in dcn32_merge_pipes_for_subvp()
116 // For now merge all pipes for SubVP since pipe split case isn't supported yet in dcn32_merge_pipes_for_subvp()
118 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */ in dcn32_merge_pipes_for_subvp()
295 * number of DET for that given plane will be split among the pipes driving that plane.
302 * among those pipes.
303 * 4. Assign the DET override to the DML pipes.
307 * @pipes: Array of DML pipes
313 display_e2e_pipe_params_st *pipes) in dcn32_determine_det_override() argument
342 /* Note: pipe_plane_count indicates the number of pipes to be used for a in dcn32_determine_det_override()
372 pipes[pipe_cnt].pipe.src.det_size_override = pipe_segments[i] * DCN3_2_DET_SEG_SIZE; in dcn32_determine_det_override()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_mall_phantom.c | 52 // Find the phantom pipes in dml2_helper_calculate_num_ways_for_subvp()
105 /* merge pipes if necessary */ in merge_pipes_for_subvp()
109 // For now merge all pipes for SubVP since pipe split case isn't supported yet in merge_pipes_for_subvp()
111 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */ in merge_pipes_for_subvp()
174 * dcn32_get_num_free_pipes: Calculate number of free pipes
183 * Number of free pipes available in the context
209 * We enter this function if we are Sub-VP capable (i.e. enough pipes available)
213 * The number of pipes used for the chosen surface must be less than or equal to the
214 * number of free pipes available.
223 * @param index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned
[all …]
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| H A D | dml2_dc_resource_mgmt.c | 142 struct dc_state *state, unsigned int plane_id, unsigned int *pipes) in find_pipes_assigned_to_plane() argument
163 pipes[num_found++] = mpc_pipe->pipe_idx; in find_pipes_assigned_to_plane()
199 // // Verify the number of pipes assigned matches in validate_pipe_assignment()
212 // // TODO: could also do additional verification that the pipes in tree are the same as in validate_pipe_assignment()
258 * However this condition comes with a caveat. We need to ignore pipes that will in find_preferred_pipe_candidates()
374 // We like to pair pipes starting from the higher order indicies for combining in find_more_pipes_for_stream()
376 // Ignore any pipes that are the preferred or last resort candidate in find_more_pipes_for_stream()
440 // We like to pair pipes starting from the higher order indicies for combining in find_more_free_pipes()
442 // Ignore any pipes that are the preferred or last resort candidate in find_more_free_pipes()
472 static void sort_pipes_for_splitting(struct dc_plane_pipe_pool *pipes) in sort_pipes_for_splitting() argument
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | resource.h | 214 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
235 * OTG Master pipe ---1--------1..N--- OPP Head pipes
237 * OPP Head pipe ---1--------0..N--- DPP pipes
241 * Plane ---1--------1..N--- DPP pipes
251 /* OTG master pipe - the master pipe of its OPP head pipes with a
252 * functional OTG. It merges all its OPP head pipes pixel data in ODM
257 * can output pixel data from its OPP head pipes' test pattern
327 * Update ODM slice count by acquiring or releasing pipes. If new slices need
332 * return - true if ODM slices are updated and required pipes are acquired. All
349 * Update MPC slice count by acquiring or releasing DPP pipes. If new slices
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.h | 45 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
55 display_e2e_pipe_params_st *pipes);
59 display_e2e_pipe_params_st *pipes,
72 struct pipe_ctx *pipes,
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| /linux/sound/sparc/ |
| H A D | dbri.c | 31 * memory and a serial device (long pipes, no. 0-15) or between two serial
32 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
33 * device (short pipes).
36 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
313 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */ member
364 #define D_PAUSE 0x1 /* Flush long pipes */
421 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */
575 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
768 /* Initialize pipes */ in dbri_initialize()
770 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1; in dbri_initialize()
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| /linux/drivers/gpu/drm/tidss/ |
| H A D | tidss_kms.c | 120 struct pipe pipes[TIDSS_MAX_PORTS]; in tidss_dispc_modeset_init() local
177 pipes[num_pipes].hw_videoport = i; in tidss_dispc_modeset_init()
178 pipes[num_pipes].bridge = bridge; in tidss_dispc_modeset_init()
179 pipes[num_pipes].enc_type = enc_type; in tidss_dispc_modeset_init()
204 tcrtc = tidss_crtc_create(tidss, pipes[i].hw_videoport, in tidss_dispc_modeset_init()
213 ret = tidss_encoder_create(tidss, pipes[i].bridge, in tidss_dispc_modeset_init()
214 pipes[i].enc_type, in tidss_dispc_modeset_init()
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| /linux/drivers/net/wireless/ath/ath6kl/ |
| H A D | usb.c | 29 /* tx/rx pipes for usb */
70 struct ath6kl_usb_pipe pipes[ATH6KL_USB_PIPE_MAX]; member
255 ath6kl_usb_free_pipe_resources(&ar_usb->pipes[i]); in ath6kl_usb_cleanup_pipe_resources()
313 ath6kl_dbg(ATH6KL_DBG_USB, "setting up USB Pipes using interface\n"); in ath6kl_usb_setup_pipe_resources()
315 /* walk descriptors and setup pipes */ in ath6kl_usb_setup_pipe_resources()
358 pipe = &ar_usb->pipes[pipe_num]; in ath6kl_usb_setup_pipe_resources()
474 if (ar_usb->pipes[i].ar_usb != NULL) in ath6kl_usb_flush_all()
475 usb_kill_anchored_urbs(&ar_usb->pipes[i].urb_submitted); in ath6kl_usb_flush_all()
489 * ar_usb->pipes[ATH6KL_USB_PIPE_RX_CTRL].urb_cnt_thresh = in ath6kl_usb_start_recv_pipes()
490 * ar_usb->pipes[ATH6KL_USB_PIPE_RX_CTRL].urb_alloc/2; in ath6kl_usb_start_recv_pipes()
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| /linux/drivers/staging/media/atomisp/pci/ |
| H A D | ia_css_stream_public.h | 117 to system memory and run pipes in offline mode */
157 * create the internal structures and fill in the configuration data and pipes
162 * @param[in] num_pipes The number of pipes to incorporate in the stream.
163 * @param[in] pipes The pipes.
167 * This function will create a stream with a given configuration and given pipes.
172 struct ia_css_pipe *pipes[],
213 * NOTE: this function will send stop event to pipes belong to this
232 * Destroy the stream and all the pipes related to it.
462 * update all pipes in the stream.
466 * stream. For image pipes that do not execute any ISP filters, this
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