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14 …he total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom…21 …by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issue…28 …unctions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issue…42 …counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA function…49 … issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issue…56 …he SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issue…70 …ts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA function…77 …ued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issue…84 …EA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issue…98 …ts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES function…[all …]
16 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…25 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…34 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…43 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…52 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…61 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…70 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…79 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…88 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…97 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…[all …]
28 …demand data translation table walks caused by a miss in the L2 TLB and performing at least one mem…32 …instruction translation table walks caused by a miss in the L2 TLB and performing at least one mem…92 …mber of memory accesses triggered by a data translation table walk and performing an update of a t…96 …memory accesses triggered by an instruction translation table walk and performing an update of a t…100 … memory accesses triggered by a demand data translation table walk and performing a read of a tran…104 …memory accesses triggered by an instruction translation table walk and performing a read of a tran…124 …demand data translation table walks caused by a miss in the L2 TLB and performing at least one mem…128 …instruction translation table walks caused by a miss in the L2 TLB and performing at least one mem…132 …erated data translation table walks caused by a miss in the L2 TLB and performing at least one mem…136 …instruction translation table walks caused by a miss in the L2 TLB and performing at least one mem…
28 …demand data translation table walks caused by a miss in the L2 TLB and performing at least one mem…32 …instruction translation table walks caused by a miss in the L2 TLB and performing at least one mem…44 …mber of memory accesses triggered by a data translation table walk and performing an update of a t…48 …memory accesses triggered by an instruction translation table walk and performing an update of a t…52 … memory accesses triggered by a demand data translation table walk and performing a read of a tran…56 …memory accesses triggered by an instruction translation table walk and performing a read of a tran…
20 trap to SIGBUS any code performing unaligned access (good for debugging bad36 0 A user process performing an unaligned memory access42 performing the unaligned access. This is of course47 performing the unaligned access.
38 this relationship. The highest performing initiator to a given target104 slower performing memory cached by a smaller higher performing memory. The107 higher performing memory to transparently cache access to progressively111 hierarchy. Each increasing cache level provides higher performing117 performing. In contrast, the memory cache level is centric to the last
16 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…25 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…34 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…43 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…52 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…61 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…70 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…79 …"PublicDescription": "Number of cycles spent performing core C state transitions. There is one ev…315 …"PublicDescription": "Number of cycles spent performing core C state transitions across all cores.…
99 * Halting simply requires that the secondary CPUs stop performing any111 * Power-off simply requires that the secondary CPUs stop performing any124 * Restart requires that the secondary CPUs stop performing any activity
85 Performing a reset makes all lines initialized to their input (pulled-up)104 # Performing a reset reinitializes all lines to a known state which
128 * Policy for performing sctp/socket accounting135 * Policy for performing sctp/socket accounting
61 An attack can be mounted on affected processors by performing a series of CALL70 targets by performing a sequence of CALL instructions.
28 …demand data translation table walks caused by a miss in the L2 TLB and performing at least one mem…32 …instruction translation table walks caused by a miss in the L2 TLB and performing at least one mem…
71 * against the value of the cpu_id field before performing a rseq85 * with the cpu_id_start value previously read, before performing
10 * that is called as part of performing resync/recovery/reshape.173 /* During a reshape we might be performing IO on the
157 when performing error recovery actions.180 If an error message indicates a non-fatal error, performing link reset196 a hierarchy in question. Then, performing link reset at upstream is