Home
last modified time | relevance | path

Searched full:pclk (Results 1 – 15 of 15) sorted by relevance

/qemu/hw/timer/
H A Dcmsdk-apb-timer.c20 * of EXTIN clock, not PCLK frequency). We don't model this.
212 ptimer_set_period_from_clock(s->timer, s->pclk, 1); in cmsdk_apb_timer_clk_update()
225 s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", in cmsdk_apb_timer_init()
233 if (!clock_has_source(s->pclk)) { in cmsdk_apb_timer_realize()
234 error_setg(errp, "CMSDK APB timer: pclk clock must be connected"); in cmsdk_apb_timer_realize()
245 ptimer_set_period_from_clock(s->timer, s->pclk, 1); in cmsdk_apb_timer_realize()
255 VMSTATE_CLOCK(pclk, CMSDKAPBTimer),
/qemu/include/hw/timer/
H A Dcmsdk-apb-timer.h25 * + Clock input "pclk": clock for the timer
37 Clock *pclk; member
/qemu/include/hw/misc/
H A Dsifive_u_otp.h71 uint32_t pclk; member
H A Daspeed_scu.h105 * 25:23 APB PCLK divider selection
368 * 11:8 APB Bus PCLK divider selection
/qemu/hw/misc/
H A Dsifive_u_otp.c55 return s->pclk; in sifive_u_otp_read()
123 s->pclk = val32; in sifive_u_otp_write()
/qemu/hw/arm/
H A Dmps2.c304 qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ); in mps2_common_init()
348 qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ); in mps2_common_init()
377 qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk); in mps2_common_init()
H A Dvirt.c320 qemu_fdt_add_subnode(fdt, "/apb-pclk"); in create_fdt()
321 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); in create_fdt()
322 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); in create_fdt()
323 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); in create_fdt()
324 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", in create_fdt()
326 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); in create_fdt()
H A Dmps3r.c341 qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ); in create_uart()
H A Dxlnx-versal-virt.c292 const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk"; in fdt_add_gem_nodes()
H A Dmps2-tz.c447 qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->apb_periph_frq); in make_uart()
H A Darmsse.c1258 qdev_connect_clock_in(DEVICE(sbd), "pclk", in armsse_realize()
/qemu/hw/char/
H A Dcmsdk-apb-uart.c340 error_setg(errp, "CMSDK APB UART: pclk-frq property must be set"); in cmsdk_apb_uart_realize()
382 DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBUART, pclk_frq, 0),
/qemu/tests/qtest/
H A Dstm32l4x5_usart-test.c165 /* Set PCLK as the clock for USART1(cf p.272) i.e. reset both bits */ in init_clocks()
/qemu/hw/rx/
H A Drx62n.c234 /* PCLK range: 8-50 MHz */ in rx62n_realize()
/qemu/hw/riscv/
H A Dsifive_u.c106 static const char * const ethclk_names[2] = { "pclk", "hclk" }; in create_fdt()