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/qemu/migration/
H A Dtrace-events238 qemu_rdma_register_odp_mr(const char *name) "Try to register On-Demand Paging memory region: %s"
/qemu/hw/arm/
H A Dmusca.c637 * though we could in theory expose a machine property on the command in musca_b1_class_init()
H A Darmv7m.c622 /* CPU objects (unlike devices) are not automatically reset on system in armv7m_load_kernel()
/qemu/hw/virtio/
H A Dvhost-shadow-virtqueue.c598 * Called on BQL context.
/qemu/target/i386/
H A Dcpu-dump.c319 s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off", in x86_cpu_dump_local_apic_state()
/qemu/hw/acpi/
H A Dcpu.c415 * on reboot system is in new mode and writing 0 in build_cpus_aml()
/qemu/hw/mips/
H A Dloongson3_virt.c22 * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with
/qemu/hw/core/
H A Dqdev.c504 * in device_unrealize due to its usage later on in the unplug path in device_set_realized()
/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
/qemu/hw/intc/
H A Darm_gicv3_common.c378 * on the GIC revision: notably, the in-kernel KVM GIC doesn't in arm_gicv3_common_realize()
/qemu/hw/misc/
H A Diotkit-secctl.c331 /* Update the combined MSC IRQ, based on S_MSCEXP_STATUS and S_MSCEXP_EN */ in iotkit_secctl_update_msc_irq()
/qemu/target/arm/tcg/
H A Dtranslate-m-nocp.c288 * branch to label based on it: in gen_branch_fpInactive()
H A Dmve_helper.c67 * the vector on the final iteration of the loop in mve_element_mask()
272 * Address writeback happens on the odd beats and updates the address
712 * to select the correct implementation based on the type of D.
2432 /* Operate on 64-bit values, but saturate at 48 bits */
2468 /* Operate on 64-bit values, but saturate at 48 bits */
/qemu/target/mips/tcg/
H A Dmsa_translate.c135 * The MSA vector registers are mapped on the in msa_translate_init()
/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
/qemu/hw/dma/
H A Dxlnx_csu_dma.c4 * This implementation is based on
/qemu/target/s390x/
H A Dioinst.c127 /* MBA uses words 10 and 11, it means align on 2**6 */ in ioinst_schib_valid()
/qemu/disas/
H A Dmips.c1223 However, "bposge32" is a branch instruction that depends on the "pos"
1266 them first. The assemblers uses a hash table based on the
2302 /* dctr and dctw are used on the r5000. */
2440 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
2454 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
3180 /* No hazard protection on coprocessor instructions--they shouldn't
4083 /* This is running out on a target machine, not in a host tool. in set_default_mips_dis_options()
4217 /* Go on to the next one. If option_end points to a comma, it in parse_mips_dis_options()
4679 /* For gdb disassembler, force odd address on jalx. */ in print_insn_args()
4716 else /* Bogus, result depends on processor. */ in print_insn_args()
[all …]
/qemu/tests/qemu-iotests/
H A D017.out269 No errors were found on the image.
539 No errors were found on the image.
1076 No errors were found on the image.
H A D018.out269 No errors were found on the image.
539 No errors were found on the image.
1076 No errors were found on the image.
/qemu/target/alpha/
H A Dtranslate.c994 emulated with a right-shift on the expanded byte mask. This in gen_msk_h()
2881 /* ??? Every TB begins with unset rounding mode, to be initialized on in alpha_tr_init_disas_context()
2894 /* Bound the number of insns to execute to those left on the page. */ in alpha_tr_init_disas_context()
/qemu/hw/xen/
H A Dxen-hvm-common.c597 * have the opportunity to pick up on the reset before the in cpu_handle_ioreq()
/qemu/util/
H A Dvfio-helpers.c94 * is recycled. The caller should make sure I/O's depending on these
/qemu/hw/input/
H A Dpckbd.c130 * OSes typically write 0xdd/0xdf to turn the A20 line off and on.

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