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/linux-6.8/drivers/clk/ingenic/
Dcgu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
27 * @n_shift: the number of bits to shift the divider value by (ie. the
28 * index of the lowest bit of the divider value in the PLL's
30 * @n_bits: the size of the divider field in bits
31 * @n_offset: the divider value which encodes to 0 in the PLL's control
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
[all …]
/linux-6.8/drivers/clk/bcm/
Dclk-kona.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
55 #define hyst_exists(hyst) ((hyst)->offset != 0)
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Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
27 /* Produces a mask of set bits covering a range of a 32-bit value */
30 return ((1 << width) - 1) << shift; in bitfield_mask()
47 /* Divider and scaling helpers */
49 /* Convert a divider into the scaled divisor value it represents. */
52 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
56 * Build a scaled divider value as close as possible to the
68 combined <<= div->u.s.frac_width; in scaled_div_build()
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Dclk-kona-setup.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "clk-kona.h"
13 #define selector_clear_exists(sel) ((sel)->width = 0)
20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
45 struct peri_clk_data *peri = bcm_clk->u.peri; in clk_requires_trigger()
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/linux-6.8/drivers/clk/baikal-t1/
Dccu-div.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Baikal-T1 CCU Dividers interface driver
10 #include <linux/clk-provider.h>
17 * CCU Divider private clock IDs
21 #define CCU_SYS_SATA_CLK -1
22 #define CCU_SYS_XGMAC_CLK -2
25 * CCU Divider private flags
26 * @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as
28 * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
30 * @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
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Dccu-div.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU Dividers interface driver
12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
19 #include <linux/clk-provider.h>
27 #include "ccu-div.h"
35 GENMASK((_width) + CCU_DIV_CTL_CLKDIV_FLD - 1, CCU_DIV_CTL_CLKDIV_FLD)
48 * getter available with non-constant mask support.
78 unsigned long divider) in ccu_div_var_update_clkdiv() argument
85 nd = ccu_div_lock_delay_ns(parent_rate, divider); in ccu_div_var_update_clkdiv()
87 if (div->features & CCU_DIV_LOCK_SHIFTED) in ccu_div_var_update_clkdiv()
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/linux-6.8/drivers/clk/ti/
Ddivider.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Divider Clock
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
26 for (clkt = table; clkt->div; clkt++) in _get_table_div()
27 if (clkt->val == val) in _get_table_div()
28 return clkt->div; in _get_table_div()
32 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
38 if (divider->table) { in _setup_mask()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
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/linux-6.8/drivers/media/i2c/cx25840/
Dcx25840-ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/drv-intf/cx25840.h>
14 #include <media/rc-core.h>
16 #include "cx25840-core.h"
117 return state ? state->ir_state : NULL; in to_ir_state()
122 * Rx and Tx Clock Divider register computations
124 * Note the largest clock divider value of 0xffff corresponds to:
135 d--; in count_to_clock_divider()
145 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
147 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
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/linux-6.8/drivers/media/pci/cx23885/
Dcx23888-ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include "cx23888-ir.h"
16 #include <media/v4l2-device.h>
17 #include <media/rc-core.h>
161 * Rx and Tx Clock Divider register computations
163 * Note the largest clock divider value of 0xffff corresponds to:
174 d--; in count_to_clock_divider()
184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
186 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
189 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
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/linux-6.8/drivers/clk/zynqmp/
Ddivider.c1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC Divider support
5 * Copyright (C) 2016-2019 Xilinx
7 * Adjustable divider clock implementation
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
16 * DOC: basic adjustable divider clock that cannot gate
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
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/linux-6.8/arch/arm/boot/dts/ti/omap/
Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
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Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
25 #clock-cells = <0>;
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/linux-6.8/drivers/clk/imx/
Dclk-divider-gate.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
15 struct clk_divider divider; member
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()
37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate()
52 val = div_gate->cached_val; in clk_divider_gate_recalc_rate()
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/linux-6.8/arch/powerpc/boot/
Dcuboot-acadia.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Old U-boot compatibility for Acadia
23 #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
27 #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
28 #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
29 #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
36 #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
37 #define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
38 #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
39 #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
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/linux-6.8/drivers/clk/
Dclk-aspeed.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <linux/clk-provider.h>
10 #include <linux/reset-controller.h>
17 * struct aspeed_gate_data - Aspeed gated clocks
19 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
34 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
35 * @hw: handle between common and hardware-specific interfaces
38 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
40 * @flags: hardware-specific flags
59 * struct aspeed_reset - Aspeed reset controller
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Dclk-divider.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
7 * Adjustable divider clock implementation
10 #include <linux/clk-provider.h>
20 * DOC: basic adjustable divider clock that cannot gate
23 * prepare - clk_prepare only ensures that parents are prepared
24 * enable - clk_enable only ensures that parents are enabled
25 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
26 * parent - fixed parent. No clk_set_parent support
29 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument
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Dclk-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
13 #include <linux/clk-provider.h>
63 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
81 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
83 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()
84 if (pllclk->type == PLL_TYPE_PCP) { in xgene_clk_pll_recalc_rate()
113 pllclk->version); in xgene_clk_pll_recalc_rate()
135 return ERR_PTR(-ENOMEM); in xgene_register_clk_pll()
143 apmclk->version = version; in xgene_register_clk_pll()
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/linux-6.8/drivers/gpu/drm/amd/amdgpu/
Damdgpu_pll.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
33 * amdgpu_pll_reduce_ratio - fractional number reduction
70 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
75 * @post_div: post divider
76 * @fb_div_max: feedback divider maximum
77 * @ref_div_max: reference divider maximum
78 * @fb_div: resulting feedback divider
79 * @ref_div: resulting reference divider
81 * Calculate feedback and reference divider for a given post divider. Makes
90 /* limit reference * post divider to a maximum */ in amdgpu_pll_get_fb_ref_div()
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/linux-6.8/drivers/gpu/drm/amd/display/dc/basics/
Dconversion.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
29 #define DIVIDER 10000 macro
31 /* S2D13 value in [-3.00...0.9999] */
32 #define S2D13_MIN (-3 * DIVIDER)
33 #define S2D13_MAX (3 * DIVIDER)
49 if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor)) in fixed_point_to_int_frac()
77 * convert_float_matrix - This converts a double into HW register spec defined format S2D13.
85 dc_fixpt_from_fraction(S2D13_MIN, DIVIDER); in convert_float_matrix()
87 dc_fixpt_from_fraction(S2D13_MAX, DIVIDER); in convert_float_matrix()
/linux-6.8/Documentation/hwmon/
Dpc87360.rst12 Datasheets: No longer available
22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
33 Note that this parameter has no effect for the PC87360, PC87363 and PC87364
42 -----------
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
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/linux-6.8/drivers/gpu/drm/i915/display/
Dintel_cdclk.c2 * Copyright © 2006-2017 Intel Corporation
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
85 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
92 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
98 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
104 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
110 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
116 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
122 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
128 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
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/linux-6.8/sound/soc/ti/
Domap-dmic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap-dmic.c -- OMAP ASoC DMIC DAI driver
5 * Copyright (C) 2010 - 2011 Texas Instruments
30 #include "omap-dmic.h"
31 #include "sdma-pcm.h"
53 writel_relaxed(val, dmic->io_base + reg); in omap_dmic_write()
58 return readl_relaxed(dmic->io_base + reg); in omap_dmic_read()
69 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled); in omap_dmic_start()
96 mutex_lock(&dmic->mutex); in omap_dmic_dai_startup()
99 dmic->active = 1; in omap_dmic_dai_startup()
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/linux-6.8/drivers/spi/
Dspi-orion.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2007-2008 Marvell Ltd.
73 * have both is for managing the armada-370-spi case with old
110 return orion_spi->base + reg; in spi_reg()
144 orion_spi = spi_controller_get_devdata(spi->controller); in orion_spi_baudrate_set()
145 devdata = orion_spi->devdata; in orion_spi_baudrate_set()
147 tclk_hz = clk_get_rate(orion_spi->clk); in orion_spi_baudrate_set()
149 if (devdata->typ == ARMADA_SPI) { in orion_spi_baudrate_set()
160 /* best integer divider: */ in orion_spi_baudrate_set()
161 unsigned divider = DIV_ROUND_UP(tclk_hz, speed); in orion_spi_baudrate_set() local
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/linux-6.8/Documentation/devicetree/bindings/timer/
Dnxp,sysctr-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bai Ping <ping.bai@nxp.com>
21 const: nxp,sysctr-timer
32 clock-names:
35 nxp,no-divider:
36 description: if present, means there is no internal base clk divider.
40 - compatible
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/linux-6.8/drivers/clk/analogbits/
Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
33 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
41 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
44 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
73 * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
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