Lines Matching +full:no +full:- +full:divider
2 * Copyright © 2006-2017 Intel Corporation
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
85 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
92 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
98 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
104 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
110 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
116 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
122 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
128 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
134 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
140 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
146 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i85x_get_cdclk()
154 if (pdev->revision == 0x1) { in i85x_get_cdclk()
155 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
159 pci_bus_read_config_word(pdev->bus, in i85x_get_cdclk()
169 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
172 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
175 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
180 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
188 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i915gm_get_cdclk()
194 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
200 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
204 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
212 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i945gm_get_cdclk()
218 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
224 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
228 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
295 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
298 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
306 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in g33_get_cdclk()
315 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
324 switch (cdclk_config->vco) { in g33_get_cdclk()
341 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
346 drm_err(&dev_priv->drm, in g33_get_cdclk()
348 cdclk_config->vco, tmp); in g33_get_cdclk()
349 cdclk_config->cdclk = 190476; in g33_get_cdclk()
355 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in pnv_get_cdclk()
362 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
365 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
368 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
371 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
374 drm_err(&dev_priv->drm, in pnv_get_cdclk()
378 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
381 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
389 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i965gm_get_cdclk()
397 cdclk_config->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
401 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; in i965gm_get_cdclk()
406 switch (cdclk_config->vco) { in i965gm_get_cdclk()
420 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
425 drm_err(&dev_priv->drm, in i965gm_get_cdclk()
427 cdclk_config->vco, tmp); in i965gm_get_cdclk()
428 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
434 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in gm45_get_cdclk()
438 cdclk_config->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
444 switch (cdclk_config->vco) { in gm45_get_cdclk()
448 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
451 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
454 drm_err(&dev_priv->drm, in gm45_get_cdclk()
456 cdclk_config->vco, tmp); in gm45_get_cdclk()
457 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
469 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
471 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
473 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
475 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
477 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
482 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? in vlv_calc_cdclk()
513 * CCK divider into the Punit register. in vlv_calc_voltage_level()
515 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
527 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
528 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
530 cdclk_config->vco); in vlv_get_cdclk()
538 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> in vlv_get_cdclk()
541 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> in vlv_get_cdclk()
554 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
565 * WA - write default credits before re-programming in vlv_program_pfi_credits()
578 drm_WARN_ON(&dev_priv->drm, in vlv_program_pfi_credits()
586 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk()
587 u32 val, cmd = cdclk_config->voltage_level; in vlv_set_cdclk()
622 drm_err(&dev_priv->drm, in vlv_set_cdclk()
627 u32 divider; in vlv_set_cdclk() local
629 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
630 cdclk) - 1; in vlv_set_cdclk()
632 /* adjust cdclk divider */ in vlv_set_cdclk()
635 val |= divider; in vlv_set_cdclk()
639 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), in vlv_set_cdclk()
641 drm_err(&dev_priv->drm, in vlv_set_cdclk()
645 /* adjust self-refresh exit latency value */ in vlv_set_cdclk()
675 int cdclk = cdclk_config->cdclk; in chv_set_cdclk()
676 u32 val, cmd = cdclk_config->voltage_level; in chv_set_cdclk()
706 drm_err(&dev_priv->drm, in chv_set_cdclk()
753 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
755 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
757 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
759 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
761 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
763 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
769 cdclk_config->voltage_level = in bdw_get_cdclk()
770 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
794 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk()
797 if (drm_WARN(&dev_priv->drm, in bdw_set_cdclk()
806 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); in bdw_set_cdclk()
808 drm_err(&dev_priv->drm, in bdw_set_cdclk()
822 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); in bdw_set_cdclk()
832 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
834 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
835 cdclk_config->voltage_level); in bdw_set_cdclk()
838 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); in bdw_set_cdclk()
883 cdclk_config->ref = 24000; in skl_dpll0_update()
884 cdclk_config->vco = 0; in skl_dpll0_update()
890 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) in skl_dpll0_update()
895 if (drm_WARN_ON(&dev_priv->drm, in skl_dpll0_update()
907 cdclk_config->vco = 8100000; in skl_dpll0_update()
911 cdclk_config->vco = 8640000; in skl_dpll0_update()
926 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
928 if (cdclk_config->vco == 0) in skl_get_cdclk()
933 if (cdclk_config->vco == 8640000) { in skl_get_cdclk()
936 cdclk_config->cdclk = 432000; in skl_get_cdclk()
939 cdclk_config->cdclk = 308571; in skl_get_cdclk()
942 cdclk_config->cdclk = 540000; in skl_get_cdclk()
945 cdclk_config->cdclk = 617143; in skl_get_cdclk()
954 cdclk_config->cdclk = 450000; in skl_get_cdclk()
957 cdclk_config->cdclk = 337500; in skl_get_cdclk()
960 cdclk_config->cdclk = 540000; in skl_get_cdclk()
963 cdclk_config->cdclk = 675000; in skl_get_cdclk()
976 cdclk_config->voltage_level = in skl_get_cdclk()
977 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
980 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
983 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); in skl_cdclk_decimal()
989 bool changed = dev_priv->skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
991 dev_priv->skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
999 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_link_rate()
1030 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
1032 dev_priv->display.cdclk.hw.vco = vco; in skl_dpll0_enable()
1044 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
1046 dev_priv->display.cdclk.hw.vco = 0; in skl_dpll0_disable()
1054 drm_WARN_ON(&dev_priv->drm, in skl_cdclk_freq_sel()
1055 cdclk != dev_priv->display.cdclk.hw.bypass); in skl_cdclk_freq_sel()
1056 drm_WARN_ON(&dev_priv->drm, vco != 0); in skl_cdclk_freq_sel()
1076 int cdclk = cdclk_config->cdclk; in skl_set_cdclk()
1077 int vco = cdclk_config->vco; in skl_set_cdclk()
1089 drm_WARN_ON_ONCE(&dev_priv->drm, in skl_set_cdclk()
1092 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1097 drm_err(&dev_priv->drm, in skl_set_cdclk()
1104 if (dev_priv->display.cdclk.hw.vco != 0 && in skl_set_cdclk()
1105 dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1110 if (dev_priv->display.cdclk.hw.vco != vco) { in skl_set_cdclk()
1122 if (dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1138 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1139 cdclk_config->voltage_level); in skl_set_cdclk()
1149 * check if the pre-os initialized the display in skl_sanitize_cdclk()
1151 * pre-os which can be used by the OS drivers to check the status in skl_sanitize_cdclk()
1157 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1160 if (dev_priv->display.cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1161 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in skl_sanitize_cdclk()
1167 * decimal part is programmed wrong from BIOS where pre-os does not in skl_sanitize_cdclk()
1172 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); in skl_sanitize_cdclk()
1178 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1181 dev_priv->display.cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1183 dev_priv->display.cdclk.hw.vco = ~0; in skl_sanitize_cdclk()
1192 if (dev_priv->display.cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1193 dev_priv->display.cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1198 if (dev_priv->skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1200 dev_priv->display.cdclk.hw.vco); in skl_cdclk_init_hw()
1204 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1206 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; in skl_cdclk_init_hw()
1217 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw()
1230 u8 divider; /* CD2X divider * 2 */ member
1235 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1236 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1237 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1238 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1239 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1244 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1245 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1246 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1251 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
1252 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1253 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1254 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
1255 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1256 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1258 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
1259 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1260 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1261 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
1262 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1263 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1265 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1266 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1267 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1268 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1269 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1270 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1275 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
1276 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
1277 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
1278 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
1279 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
1280 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
1282 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
1283 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
1284 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
1285 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
1286 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
1287 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
1289 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
1290 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
1291 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
1292 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
1293 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
1294 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
1299 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1300 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1301 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1303 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1304 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1305 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
1307 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1308 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1309 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1314 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1315 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1316 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1317 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1318 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1320 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1321 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1322 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1323 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1324 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1326 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1327 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1328 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1329 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1330 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1335 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1336 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1337 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1338 { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
1339 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1340 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1342 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1343 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1344 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1345 { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
1346 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1347 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1349 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1350 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1351 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1352 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
1353 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1354 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1359 { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
1360 { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
1361 { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
1362 { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
1363 { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
1364 { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
1365 { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
1366 { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
1367 { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
1368 { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
1369 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
1370 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
1371 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
1376 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
1377 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
1378 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
1379 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
1380 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
1381 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
1386 { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
1387 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
1388 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
1389 { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
1390 { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
1391 { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
1392 { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
1393 { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
1394 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
1395 { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
1396 { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
1397 { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
1398 { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
1399 { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
1400 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
1401 { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
1402 { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
1403 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
1404 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
1405 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
1406 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
1412 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk()
1416 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk()
1420 drm_WARN(&dev_priv->drm, 1, in bxt_calc_cdclk()
1422 min_cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk()
1428 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk_pll_vco()
1431 if (cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1435 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1437 return dev_priv->display.cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1439 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1440 cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1460 return num_voltage_levels - 1; in calc_voltage_level()
1532 cdclk_config->ref = 24000; in icl_readout_refclk()
1535 cdclk_config->ref = 19200; in icl_readout_refclk()
1538 cdclk_config->ref = 38400; in icl_readout_refclk()
1549 cdclk_config->ref = 38400; in bxt_de_pll_readout()
1553 cdclk_config->ref = 19200; in bxt_de_pll_readout()
1562 cdclk_config->vco = 0; in bxt_de_pll_readout()
1575 cdclk_config->vco = ratio * cdclk_config->ref; in bxt_de_pll_readout()
1582 u32 divider; in bxt_get_cdclk() local
1588 cdclk_config->bypass = cdclk_config->ref / 2; in bxt_get_cdclk()
1590 cdclk_config->bypass = 50000; in bxt_get_cdclk()
1592 cdclk_config->bypass = cdclk_config->ref; in bxt_get_cdclk()
1594 if (cdclk_config->vco == 0) { in bxt_get_cdclk()
1595 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1599 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; in bxt_get_cdclk()
1601 switch (divider) { in bxt_get_cdclk()
1615 MISSING_CASE(divider); in bxt_get_cdclk()
1627 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); in bxt_get_cdclk()
1629 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * in bxt_get_cdclk()
1630 cdclk_config->vco, size * div); in bxt_get_cdclk()
1632 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1640 cdclk_config->voltage_level = in bxt_get_cdclk()
1641 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); in bxt_get_cdclk()
1651 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); in bxt_de_pll_disable()
1653 dev_priv->display.cdclk.hw.vco = 0; in bxt_de_pll_disable()
1658 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in bxt_de_pll_enable()
1668 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); in bxt_de_pll_enable()
1670 dev_priv->display.cdclk.hw.vco = vco; in bxt_de_pll_enable()
1680 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1682 dev_priv->display.cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1687 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in icl_cdclk_pll_enable()
1698 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1700 dev_priv->display.cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1705 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1719 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); in adlp_cdclk_pll_crawl()
1724 dev_priv->display.cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1753 drm_WARN_ON(&dev_priv->drm, in bxt_cdclk_cd2x_div_sel()
1754 cdclk != dev_priv->display.cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1755 drm_WARN_ON(&dev_priv->drm, vco != 0); in bxt_cdclk_cd2x_div_sel()
1771 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in cdclk_squash_waveform()
1774 if (cdclk == dev_priv->display.cdclk.hw.bypass) in cdclk_squash_waveform()
1778 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in cdclk_squash_waveform()
1782 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1783 cdclk, dev_priv->display.cdclk.hw.ref); in cdclk_squash_waveform()
1790 if (i915->display.cdclk.hw.vco != 0 && in icl_cdclk_pll_update()
1791 i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1794 if (i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1800 if (i915->display.cdclk.hw.vco != 0 && in bxt_cdclk_pll_update()
1801 i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1804 if (i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1845 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ in cdclk_compute_crawl_and_squash_midpoint()
1846 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) in cdclk_compute_crawl_and_squash_midpoint()
1853 old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
1854 new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
1857 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || in cdclk_compute_crawl_and_squash_midpoint()
1858 old_cdclk_config->vco == new_cdclk_config->vco || in cdclk_compute_crawl_and_squash_midpoint()
1866 * - If moving to a higher cdclk, the desired action is squashing. in cdclk_compute_crawl_and_squash_midpoint()
1868 * - If moving to a lower cdclk, the desired action is crawling. in cdclk_compute_crawl_and_squash_midpoint()
1873 mid_cdclk_config->vco = old_cdclk_config->vco; in cdclk_compute_crawl_and_squash_midpoint()
1876 mid_cdclk_config->vco = new_cdclk_config->vco; in cdclk_compute_crawl_and_squash_midpoint()
1880 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * in cdclk_compute_crawl_and_squash_midpoint()
1881 mid_cdclk_config->vco, in cdclk_compute_crawl_and_squash_midpoint()
1886 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk < in cdclk_compute_crawl_and_squash_midpoint()
1887 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); in cdclk_compute_crawl_and_squash_midpoint()
1888 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk > in cdclk_compute_crawl_and_squash_midpoint()
1889 i915->display.cdclk.max_cdclk_freq); in cdclk_compute_crawl_and_squash_midpoint()
1890 drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) != in cdclk_compute_crawl_and_squash_midpoint()
1901 dev_priv->display.cdclk.hw.vco > 0; in pll_enable_wa_needed()
1908 int cdclk = cdclk_config->cdclk; in _bxt_set_cdclk()
1909 int vco = cdclk_config->vco; in _bxt_set_cdclk()
1914 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
1915 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { in _bxt_set_cdclk()
1916 if (dev_priv->display.cdclk.hw.vco != vco) in _bxt_set_cdclk()
1962 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk()
1974 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
1983 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
1988 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1994 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, in bxt_set_cdclk()
2004 * NOOP - No Pcode communication needed for in bxt_set_cdclk()
2008 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
2009 cdclk_config->voltage_level); in bxt_set_cdclk()
2017 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
2019 cdclk_config->voltage_level, in bxt_set_cdclk()
2023 drm_err(&dev_priv->drm, in bxt_set_cdclk()
2036 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
2045 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
2047 if (dev_priv->display.cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
2048 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_sanitize_cdclk()
2066 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2067 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2072 if (vco != dev_priv->display.cdclk.hw.vco) in bxt_sanitize_cdclk()
2077 /* Figure out what CD2X divider we should be using for this cdclk */ in bxt_sanitize_cdclk()
2079 clock = dev_priv->display.cdclk.hw.vco / 2; in bxt_sanitize_cdclk()
2081 clock = dev_priv->display.cdclk.hw.cdclk; in bxt_sanitize_cdclk()
2084 dev_priv->display.cdclk.hw.vco); in bxt_sanitize_cdclk()
2091 dev_priv->display.cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
2099 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
2102 dev_priv->display.cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
2105 dev_priv->display.cdclk.hw.vco = ~0; in bxt_sanitize_cdclk()
2114 if (dev_priv->display.cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2115 dev_priv->display.cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2118 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
2122 * - The initial CDCLK needs to be read from VBT. in bxt_cdclk_init_hw()
2135 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw()
2146 * intel_cdclk_init_hw - Initialize CDCLK hardware
2149 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
2163 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2184 drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco)); in intel_cdclk_can_crawl_and_squash()
2186 if (a->vco == 0 || b->vco == 0) in intel_cdclk_can_crawl_and_squash()
2192 old_waveform = cdclk_squash_waveform(i915, a->cdclk); in intel_cdclk_can_crawl_and_squash()
2193 new_waveform = cdclk_squash_waveform(i915, b->cdclk); in intel_cdclk_can_crawl_and_squash()
2195 return a->vco != b->vco && in intel_cdclk_can_crawl_and_squash()
2209 * The vco and cd2x divider will change independently in intel_cdclk_can_crawl()
2212 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); in intel_cdclk_can_crawl()
2213 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); in intel_cdclk_can_crawl()
2215 return a->vco != 0 && b->vco != 0 && in intel_cdclk_can_crawl()
2216 a->vco != b->vco && in intel_cdclk_can_crawl()
2218 a->ref == b->ref; in intel_cdclk_can_crawl()
2227 * to differentiate squasher vs. cd2x divider properly. For in intel_cdclk_can_squash()
2229 * divider. in intel_cdclk_can_squash()
2234 return a->cdclk != b->cdclk && in intel_cdclk_can_squash()
2235 a->vco != 0 && in intel_cdclk_can_squash()
2236 a->vco == b->vco && in intel_cdclk_can_squash()
2237 a->ref == b->ref; in intel_cdclk_can_squash()
2241 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
2253 return a->cdclk != b->cdclk || in intel_cdclk_needs_modeset()
2254 a->vco != b->vco || in intel_cdclk_needs_modeset()
2255 a->ref != b->ref; in intel_cdclk_needs_modeset()
2259 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2260 * configurations requires only a cd2x divider update
2267 * can be done with just a cd2x divider update, false if not.
2279 * to differentiate squasher vs. cd2x divider properly. For in intel_cdclk_can_cd2x_update()
2281 * divider. in intel_cdclk_can_cd2x_update()
2286 return a->cdclk != b->cdclk && in intel_cdclk_can_cd2x_update()
2287 a->vco != 0 && in intel_cdclk_can_cd2x_update()
2288 a->vco == b->vco && in intel_cdclk_can_cd2x_update()
2289 a->ref == b->ref; in intel_cdclk_can_cd2x_update()
2293 * intel_cdclk_changed - Determine if two CDCLK configurations are different
2304 a->voltage_level != b->voltage_level; in intel_cdclk_changed()
2311 drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", in intel_cdclk_dump_config()
2312 context, cdclk_config->cdclk, cdclk_config->vco, in intel_cdclk_dump_config()
2313 cdclk_config->ref, cdclk_config->bypass, in intel_cdclk_dump_config()
2314 cdclk_config->voltage_level); in intel_cdclk_dump_config()
2338 ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL, in intel_pcode_notify()
2344 drm_err(&i915->drm, in intel_pcode_notify()
2350 * intel_set_cdclk - Push the CDCLK configuration to the hardware
2364 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2367 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2372 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
2385 mutex_lock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2386 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
2389 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, in intel_set_cdclk()
2390 &dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2395 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
2398 mutex_unlock(&intel_dp->aux.hw_mutex); in intel_set_cdclk()
2400 mutex_unlock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2402 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
2410 if (drm_WARN(&dev_priv->drm, in intel_set_cdclk()
2411 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2413 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); in intel_set_cdclk()
2420 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_cdclk_pcode_pre_notify()
2428 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_cdclk_pcode_pre_notify()
2429 &new_cdclk_state->actual) && in intel_cdclk_pcode_pre_notify()
2430 new_cdclk_state->active_pipes == in intel_cdclk_pcode_pre_notify()
2431 old_cdclk_state->active_pipes) in intel_cdclk_pcode_pre_notify()
2437 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_pre_notify()
2438 update_pipe_count = hweight8(new_cdclk_state->active_pipes) > in intel_cdclk_pcode_pre_notify()
2439 hweight8(old_cdclk_state->active_pipes); in intel_cdclk_pcode_pre_notify()
2448 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); in intel_cdclk_pcode_pre_notify()
2454 * no action if it is decreasing, before the change in intel_cdclk_pcode_pre_notify()
2457 num_active_pipes = hweight8(new_cdclk_state->active_pipes); in intel_cdclk_pcode_pre_notify()
2465 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_cdclk_pcode_post_notify()
2474 voltage_level = new_cdclk_state->actual.voltage_level; in intel_cdclk_pcode_post_notify()
2476 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2477 update_pipe_count = hweight8(new_cdclk_state->active_pipes) < in intel_cdclk_pcode_post_notify()
2478 hweight8(old_cdclk_state->active_pipes); in intel_cdclk_pcode_post_notify()
2485 cdclk = new_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2491 * no action if it is increasing, after the change in intel_cdclk_pcode_post_notify()
2494 num_active_pipes = hweight8(new_cdclk_state->active_pipes); in intel_cdclk_pcode_post_notify()
2501 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2510 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_set_cdclk_pre_plane_update()
2515 enum pipe pipe = new_cdclk_state->pipe; in intel_set_cdclk_pre_plane_update()
2517 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_set_cdclk_pre_plane_update()
2518 &new_cdclk_state->actual)) in intel_set_cdclk_pre_plane_update()
2525 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { in intel_set_cdclk_pre_plane_update()
2526 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_pre_plane_update()
2528 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe); in intel_set_cdclk_pre_plane_update()
2533 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2542 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_set_cdclk_post_plane_update()
2547 enum pipe pipe = new_cdclk_state->pipe; in intel_set_cdclk_post_plane_update()
2549 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_set_cdclk_post_plane_update()
2550 &new_cdclk_state->actual)) in intel_set_cdclk_post_plane_update()
2557 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { in intel_set_cdclk_post_plane_update()
2558 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_post_plane_update()
2560 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe); in intel_set_cdclk_post_plane_update()
2566 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_pixel_rate_to_cdclk()
2567 int pixel_rate = crtc_state->pixel_rate; in intel_pixel_rate_to_cdclk()
2576 else if (crtc_state->double_wide) in intel_pixel_rate_to_cdclk()
2584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_planes_min_cdclk()
2585 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_planes_min_cdclk()
2589 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) in intel_planes_min_cdclk()
2590 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); in intel_planes_min_cdclk()
2597 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_vdsc_min_cdclk()
2598 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_vdsc_min_cdclk()
2610 DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances)); in intel_vdsc_min_cdclk()
2612 if (crtc_state->bigjoiner_pipes) { in intel_vdsc_min_cdclk()
2613 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock); in intel_vdsc_min_cdclk()
2629 (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) * in intel_vdsc_min_cdclk()
2641 to_i915(crtc_state->uapi.crtc->dev); in intel_crtc_compute_min_cdclk()
2644 if (!crtc_state->hw.enable) in intel_crtc_compute_min_cdclk()
2659 crtc_state->has_audio && in intel_crtc_compute_min_cdclk()
2660 crtc_state->port_clock >= 540000 && in intel_crtc_compute_min_cdclk()
2661 crtc_state->lane_count == 4) { in intel_crtc_compute_min_cdclk()
2675 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) in intel_crtc_compute_min_cdclk()
2686 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) in intel_crtc_compute_min_cdclk()
2687 min_cdclk = max(crtc_state->port_clock, min_cdclk); in intel_crtc_compute_min_cdclk()
2709 if (crtc_state->dsc.compression_enable) in intel_crtc_compute_min_cdclk()
2727 min_t(int, crtc_state->pixel_rate, in intel_crtc_compute_min_cdclk()
2728 dev_priv->display.cdclk.max_cdclk_freq)); in intel_crtc_compute_min_cdclk()
2736 struct intel_atomic_state *state = cdclk_state->base.state; in intel_compute_min_cdclk()
2737 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_compute_min_cdclk()
2751 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) in intel_compute_min_cdclk()
2754 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_compute_min_cdclk()
2756 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2765 if (cdclk_state->bw_min_cdclk != min_cdclk) { in intel_compute_min_cdclk()
2768 cdclk_state->bw_min_cdclk = min_cdclk; in intel_compute_min_cdclk()
2770 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2776 min_cdclk = max(cdclk_state->force_min_cdclk, in intel_compute_min_cdclk()
2777 cdclk_state->bw_min_cdclk); in intel_compute_min_cdclk()
2779 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); in intel_compute_min_cdclk()
2786 * by changing the cd2x divider (see glk_cdclk_table[]) and in intel_compute_min_cdclk()
2789 if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && in intel_compute_min_cdclk()
2790 !is_power_of_2(cdclk_state->active_pipes)) in intel_compute_min_cdclk()
2793 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2794 drm_dbg_kms(&dev_priv->drm, in intel_compute_min_cdclk()
2796 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2797 return -EINVAL; in intel_compute_min_cdclk()
2812 * Should that relationship no longer hold on
2818 struct intel_atomic_state *state = cdclk_state->base.state; in bxt_compute_min_voltage_level()
2819 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_compute_min_voltage_level()
2829 if (crtc_state->hw.enable) in bxt_compute_min_voltage_level()
2830 min_voltage_level = crtc_state->min_voltage_level; in bxt_compute_min_voltage_level()
2834 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) in bxt_compute_min_voltage_level()
2837 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; in bxt_compute_min_voltage_level()
2839 ret = intel_atomic_lock_global_state(&cdclk_state->base); in bxt_compute_min_voltage_level()
2846 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], in bxt_compute_min_voltage_level()
2854 struct intel_atomic_state *state = cdclk_state->base.state; in vlv_modeset_calc_cdclk()
2855 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in vlv_modeset_calc_cdclk()
2864 cdclk_state->logical.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2865 cdclk_state->logical.voltage_level = in vlv_modeset_calc_cdclk()
2868 if (!cdclk_state->active_pipes) { in vlv_modeset_calc_cdclk()
2869 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2871 cdclk_state->actual.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2872 cdclk_state->actual.voltage_level = in vlv_modeset_calc_cdclk()
2875 cdclk_state->actual = cdclk_state->logical; in vlv_modeset_calc_cdclk()
2891 cdclk_state->logical.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2892 cdclk_state->logical.voltage_level = in bdw_modeset_calc_cdclk()
2895 if (!cdclk_state->active_pipes) { in bdw_modeset_calc_cdclk()
2896 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); in bdw_modeset_calc_cdclk()
2898 cdclk_state->actual.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2899 cdclk_state->actual.voltage_level = in bdw_modeset_calc_cdclk()
2902 cdclk_state->actual = cdclk_state->logical; in bdw_modeset_calc_cdclk()
2910 struct intel_atomic_state *state = cdclk_state->base.state; in skl_dpll0_vco()
2911 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in skl_dpll0_vco()
2916 vco = cdclk_state->logical.vco; in skl_dpll0_vco()
2918 vco = dev_priv->skl_preferred_vco_freq; in skl_dpll0_vco()
2921 if (!crtc_state->hw.enable) in skl_dpll0_vco()
2931 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()
2957 cdclk_state->logical.vco = vco; in skl_modeset_calc_cdclk()
2958 cdclk_state->logical.cdclk = cdclk; in skl_modeset_calc_cdclk()
2959 cdclk_state->logical.voltage_level = in skl_modeset_calc_cdclk()
2962 if (!cdclk_state->active_pipes) { in skl_modeset_calc_cdclk()
2963 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); in skl_modeset_calc_cdclk()
2965 cdclk_state->actual.vco = vco; in skl_modeset_calc_cdclk()
2966 cdclk_state->actual.cdclk = cdclk; in skl_modeset_calc_cdclk()
2967 cdclk_state->actual.voltage_level = in skl_modeset_calc_cdclk()
2970 cdclk_state->actual = cdclk_state->logical; in skl_modeset_calc_cdclk()
2978 struct intel_atomic_state *state = cdclk_state->base.state; in bxt_modeset_calc_cdclk()
2979 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_modeset_calc_cdclk()
2993 cdclk_state->logical.vco = vco; in bxt_modeset_calc_cdclk()
2994 cdclk_state->logical.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2995 cdclk_state->logical.voltage_level = in bxt_modeset_calc_cdclk()
2999 if (!cdclk_state->active_pipes) { in bxt_modeset_calc_cdclk()
3000 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
3003 cdclk_state->actual.vco = vco; in bxt_modeset_calc_cdclk()
3004 cdclk_state->actual.cdclk = cdclk; in bxt_modeset_calc_cdclk()
3005 cdclk_state->actual.voltage_level = in bxt_modeset_calc_cdclk()
3008 cdclk_state->actual = cdclk_state->logical; in bxt_modeset_calc_cdclk()
3034 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); in intel_cdclk_duplicate_state()
3038 cdclk_state->pipe = INVALID_PIPE; in intel_cdclk_duplicate_state()
3040 return &cdclk_state->base; in intel_cdclk_duplicate_state()
3057 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_cdclk_state()
3060 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); in intel_atomic_get_cdclk_state()
3096 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) in intel_cdclk_atomic_check()
3108 return -ENOMEM; in intel_cdclk_init()
3110 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, in intel_cdclk_init()
3111 &cdclk_state->base, &intel_cdclk_funcs); in intel_cdclk_init()
3120 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != in intel_cdclk_need_serialize()
3121 hweight8(new_cdclk_state->active_pipes); in intel_cdclk_need_serialize()
3122 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, in intel_cdclk_need_serialize()
3123 &new_cdclk_state->actual); in intel_cdclk_need_serialize()
3133 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_calc_cdclk()
3145 new_cdclk_state->active_pipes = in intel_modeset_calc_cdclk()
3146 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
3157 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
3160 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || in intel_modeset_calc_cdclk()
3161 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || in intel_modeset_calc_cdclk()
3162 intel_cdclk_changed(&old_cdclk_state->logical, in intel_modeset_calc_cdclk()
3163 &new_cdclk_state->logical)) { in intel_modeset_calc_cdclk()
3164 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
3171 if (is_power_of_2(new_cdclk_state->active_pipes) && in intel_modeset_calc_cdclk()
3173 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3174 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3178 pipe = ilog2(new_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
3181 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_modeset_calc_cdclk()
3190 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3191 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3192 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3195 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3196 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3197 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3200 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3201 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3202 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3205 new_cdclk_state->pipe = pipe; in intel_modeset_calc_cdclk()
3207 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3208 "Can change cdclk cd2x divider with pipe %c active\n", in intel_modeset_calc_cdclk()
3210 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3211 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3217 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3221 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3223 new_cdclk_state->logical.cdclk, in intel_modeset_calc_cdclk()
3224 new_cdclk_state->actual.cdclk); in intel_modeset_calc_cdclk()
3225 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3227 new_cdclk_state->logical.voltage_level, in intel_modeset_calc_cdclk()
3228 new_cdclk_state->actual.voltage_level); in intel_modeset_calc_cdclk()
3235 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
3251 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3261 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3262 dev_priv->display.cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
3264 dev_priv->display.cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
3266 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3267 dev_priv->display.cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
3269 dev_priv->display.cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
3271 dev_priv->display.cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
3273 dev_priv->display.cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3278 vco = dev_priv->skl_preferred_vco_freq; in intel_update_max_cdclk()
3279 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
3295 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3304 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3306 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3308 dev_priv->display.cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3310 dev_priv->display.cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3312 dev_priv->display.cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3314 dev_priv->display.cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3317 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; in intel_update_max_cdclk()
3320 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); in intel_update_max_cdclk()
3322 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", in intel_update_max_cdclk()
3323 dev_priv->display.cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3325 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", in intel_update_max_cdclk()
3326 dev_priv->max_dotclk_freq); in intel_update_max_cdclk()
3330 * intel_update_cdclk - Determine the current CDCLK frequency
3337 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); in intel_update_cdclk()
3347 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3354 * "Program Numerator=2, Denominator=4, Divider=37 decimal." in dg1_rawclk()
3365 int divider, fraction; in cnp_rawclk() local
3369 divider = 24000; in cnp_rawclk()
3373 divider = 19000; in cnp_rawclk()
3377 rawclk = CNP_RAWCLK_DIV(divider / 1000); in cnp_rawclk()
3382 fraction) - 1); in cnp_rawclk()
3388 return divider + fraction; in cnp_rawclk()
3460 * intel_read_rawclk - Determine the current RAWCLK frequency
3488 /* no rawclk on other platforms, or no need to know it */ in intel_read_rawclk()
3496 struct drm_i915_private *i915 = m->private; in i915_cdclk_info_show()
3498 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); in i915_cdclk_info_show()
3499 seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); in i915_cdclk_info_show()
3500 seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq); in i915_cdclk_info_show()
3509 struct drm_minor *minor = i915->drm.primary; in intel_cdclk_debugfs_register()
3511 debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root, in intel_cdclk_debugfs_register()
3659 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3665 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; in intel_init_cdclk_hooks()
3666 dev_priv->display.cdclk.table = lnl_cdclk_table; in intel_init_cdclk_hooks()
3668 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; in intel_init_cdclk_hooks()
3669 dev_priv->display.cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3671 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3672 dev_priv->display.cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3674 /* Wa_22011320316:adl-p[a0] */ in intel_init_cdclk_hooks()
3676 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3677 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3679 dev_priv->display.cdclk.table = rplu_cdclk_table; in intel_init_cdclk_hooks()
3680 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3682 dev_priv->display.cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3683 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3686 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3687 dev_priv->display.cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3689 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3690 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3692 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3693 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3695 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3696 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3698 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3700 dev_priv->display.cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3702 dev_priv->display.cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3704 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3706 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3708 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3710 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3712 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3714 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3716 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3718 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3720 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3722 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3724 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3726 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3728 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3730 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3732 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3734 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3736 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3738 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3740 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3742 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3744 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3747 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, in intel_init_cdclk_hooks()
3749 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()