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/linux-6.8/Documentation/devicetree/bindings/net/can/
Dmicrochip,mpfs-can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/microchip,mpfs-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Microchip PolarFire SoC (MPFS) can controller
11 - Conor Dooley <conor.dooley@microchip.com>
14 - $ref: can-controller.yaml#
18 const: microchip,mpfs-can
30 - compatible
31 - reg
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/linux-6.8/drivers/soc/microchip/
Dmpfs-sys-controller.c1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip PolarFire SoC (MPFS) system controller driver
5 * Copyright (c) 2020-2021 Microchip Corporation. All rights reserved.
21 #include <soc/microchip/mpfs.h>
48 reinit_completion(&sys_controller->c); in mpfs_blocking_transaction()
50 ret = mbox_send_message(sys_controller->chan, msg); in mpfs_blocking_transaction()
52 dev_warn(sys_controller->client.dev, "MPFS sys controller service timeout\n"); in mpfs_blocking_transaction()
60 * to trigger the rx callback then the service can be deemed to have in mpfs_blocking_transaction()
62 * The caller can then interrogate msg::response::resp_status to in mpfs_blocking_transaction()
67 if (!wait_for_completion_timeout(&sys_controller->c, timeout)) { in mpfs_blocking_transaction()
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/linux-6.8/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
11 compatible = "microchip,mpfs";
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
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Dmpfs-icicle-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
6 #include "mpfs.dtsi"
7 #include "mpfs-icicle-kit-fabric.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
12 model = "Microchip PolarFire-SoC Icicle Kit";
13 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
14 "microchip,mpfs";
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/linux-6.8/Documentation/devicetree/bindings/soc/microchip/
Dmicrochip,mpfs-sys-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
10 - Conor Dooley <conor.dooley@microchip.com>
16 eNVM contents etc. More information on these services can be found online, at
17 https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
27 const: microchip,mpfs-sys-controller
29 microchip,bitstream-flash:
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/linux-6.8/drivers/net/ethernet/mellanox/mlx5/core/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 Core driver for low level functionality of the ConnectX-4 and
18 Connect-IB cards by Mellanox Technologies.
28 sandbox-specific client drivers.
36 Ethernet support in Mellanox Technologies ConnectX-4 NIC.
43 Mellanox MLX5 ethernet hardware-accelerated receive flow steering support,
57 bool "Mellanox Technologies MLX5 MPFS support"
61 Mellanox Technologies Ethernet Multi-Physical Function Switch (MPFS)
62 support in ConnectX NIC. MPFs is required for when multi-PF configuration
67 bool "Mellanox Technologies MLX5 SRIOV E-Switch support"
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Deswitch.c14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
39 #include <linux/mlx5/mpfs.h>
65 bool mpfs; /* UC MAC was added to MPFs */ member
73 return -EOPNOTSUPP; in mlx5_eswitch_check()
76 return -EOPNOTSUPP; in mlx5_eswitch_check()
92 return dev->priv.eswitch; in __mlx5_devlink_eswitch_get()
112 return ERR_PTR(-EPERM); in mlx5_eswitch_get_vport()
114 vport = xa_load(&esw->vports, vport_num); in mlx5_eswitch_get_vport()
116 esw_debug(esw->dev, "vport out of range: num(0x%x)\n", vport_num); in mlx5_eswitch_get_vport()
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Dmain.c2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
38 #include <linux/dma-mapping.h>
54 #include "lib/mpfs.h"
88 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
91 #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1)
198 fw_initializing = ioread32be(&dev->iseg->initializing); in wait_fw_init()
202 test_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { in wait_fw_init()
203 err = -EBUSY; in wait_fw_init()
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/linux-6.8/drivers/usb/musb/
Dmpfs.c1 // SPDX-License-Identifier: GPL-2.0
3 * PolarFire SoC (MPFS) MUSB Glue Layer
5 * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
11 #include <linux/dma-mapping.h>
58 spin_lock_irqsave(&musb->lock, flags); in mpfs_musb_interrupt()
60 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); in mpfs_musb_interrupt()
61 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); in mpfs_musb_interrupt()
62 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); in mpfs_musb_interrupt()
64 if (musb->int_usb || musb->int_tx || musb->int_rx) { in mpfs_musb_interrupt()
65 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb); in mpfs_musb_interrupt()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # USB Dual Role (OTG-ready) Controller Drivers
7 # (M)HDRC = (Multipoint) Highspeed Dual-Role Controller
27 module will be called "musb-hdrc".
74 tristate "DA8xx/OMAP-L1x"
123 will be called mpfs.
135 you can still disable it at run time using the "use_dma=n" module
159 depends on USB_MUSB_TUSB6010 = USB_MUSB_HDRC # both built-in or both modules
/linux-6.8/drivers/mailbox/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
16 The controller has 3 mailbox channels, the last of which can be
40 which can be used in Secure mode only.
58 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
77 This can also be changed at runtime (via the mbox_kfifo_size
84 This driver provides support for inter-processor communication
165 tristate "PolarFire SoC (MPFS) Mailbox"
169 This driver adds support for the PolarFire SoC (MPFS) mailbox controller.
172 module will be called mailbox-mpfs.
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/linux-6.8/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
Dkconfig.rst1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
10 | mlx5 core is modular and most of the major mlx5 core driver features can be selected (compiled in…
26 | The driver can be enabled by choosing CONFIG_MLX5_CORE=y/m in kernel config.
34 | built-in into mlx5_core.ko.
39 …g (DCB) Support <https://enterprise-support.nvidia.com/s/article/howto-auto-config-pfc-and-ets-on-…
53 | Flow-based classifiers, such as those registered through
54 | `tc-flower(8)`, are processed by the device, rather than the
61 | Enables Hardware-accelerated receive flow steering (arfs) support, and ntuple filtering.
62 | https://enterprise-support.nvidia.com/s/article/howto-configure-arfs-on-connectx-4
67 | Enables :ref:`IPSec XFRM cryptography-offload acceleration <xfrm_device>`.
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Dcounters.rst1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
13 - `Overview`_
14 - `Groups`_
15 - `Types`_
16 - `Descriptions`_
27 ----------------------------------------
29 ---------------------------------------- ---------------------------------------- |
32 | ------------------- --------------- | | ------------------- --------------- | |
34 | ------------------- --------------- | | ------------------- --------------- | |
36 | ------------------- | | ------------------- | |
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/linux-6.8/drivers/firmware/microchip/
Dmpfs-auto-update.c1 // SPDX-License-Identifier: GPL-2.0
8 * Copyright (c) 2022-2023 Microchip Corporation. All rights reserved.
20 #include <soc/microchip/mpfs.h>
43 * |------------------------------| 0x0000000
46 * |------------------------------| 0x0000400
50 * |------------------------------| 0x0100400
53 * |------------------------------| 0x1500400
56 * |------------------------------| 0x2900400
58 * | Reserved for multi-image IAP |
60 * |------------------------------| 0x3D00400
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/linux-6.8/drivers/spi/
Dspi-microchip-core.c1 // SPDX-License-Identifier: (GPL-2.0)
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
114 return readl(spi->regs + reg); in mchp_corespi_read()
119 writel(val, spi->regs + reg); in mchp_corespi_write()
136 fifo_max = min(spi->rx_len, FIFO_DEPTH); in mchp_corespi_read_fifo()
141 if (spi->rx_buf) in mchp_corespi_read_fifo()
142 *spi->rx_buf++ = data; in mchp_corespi_read_fifo()
145 spi->rx_len -= i; in mchp_corespi_read_fifo()
146 spi->pending -= i; in mchp_corespi_read_fifo()
192 * FRAMESUP. While both the upper and lower bits can be *READ* from the in mchp_corespi_set_xfer_size()
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/linux-6.8/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
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/linux-6.8/drivers/reset/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
101 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
160 bool "Microchip PolarFire SoC (MPFS) Reset Driver"
190 Raspberry Pi 4's co-processor controls some of the board's HW
193 interfacing with RPi4's co-processor and model these firmware
220 that can be asserted and deasserted by toggling bits in a contiguous,
224 - Altera SoCFPGAs
225 - ASPEED BMC SoCs
226 - Bitmain BM1880 SoC
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/linux-6.8/drivers/dma/sf-pdma/
Dsf-pdma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * - drivers/dma/fsl-edma.c
8 * - drivers/dma/dw-edma/
9 * - drivers/dma/pxa-dma.c
12 * - Chapter 12 "Platform DMA Engine (PDMA)" of
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
21 #include <linux/dma-mapping.h>
26 #include "sf-pdma.h"
63 desc->chan = chan; in sf_pdma_alloc_desc()
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/linux-6.8/drivers/vdpa/mlx5/net/
Dmlx5_vnet.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
20 #include <linux/mlx5/mpfs.h>
47 #define MLX5_FEATURE(_mvdev, _feature) (!!((_mvdev)->actual_features & BIT_ULL(_feature)))
137 if (!(mvdev->actual_features & BIT_ULL(VIRTIO_NET_F_MQ))) { in is_index_valid()
138 if (!(mvdev->actual_features & BIT_ULL(VIRTIO_NET_F_CTRL_VQ))) in is_index_valid()
144 return idx <= mvdev->max_idx; in is_index_valid()
168 /* TODO: cross-endian support */
172 (mvdev->actual_features & BIT_ULL(VIRTIO_F_VERSION_1)); in mlx5_vdpa_is_little_endian()
187 if (!(mvdev->actual_features & BIT_ULL(VIRTIO_NET_F_MQ))) in ctrl_vq_idx()
190 return mvdev->max_vqs; in ctrl_vq_idx()
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/linux-6.8/drivers/rtc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
44 This clock should be battery-backed, so that it reads the correct
45 time when the system boots from a power-off state. Otherwise, your
69 one can sleep when setting time, because it runs in the workqueue
129 can be accessed as /dev/rtc, which is a name
141 once-per-second update interrupts, used for synchronization.
151 RTC test driver. It's a software RTC which can be
158 This driver can also be built as a module. If so, the module
159 will be called rtc-test.
172 This driver can also be built as a module. If so, the module
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/linux-6.8/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
41 Can be useful for excluding a specific subdirectory, for instance:
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
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/linux-6.8/drivers/net/ethernet/cadence/
Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
40 #include <linux/firmware/xlnx-zynqmp.h>
57 * (bp)->rx_ring_size)
63 * (bp)->tx_ring_size)
66 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
77 …MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN -…
94 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
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