Lines Matching +full:mpfs +full:- +full:can
1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
16 The controller has 3 mailbox channels, the last of which can be
40 which can be used in Secure mode only.
58 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
77 This can also be changed at runtime (via the mbox_kfifo_size
84 This driver provides support for inter-processor communication
165 tristate "PolarFire SoC (MPFS) Mailbox"
169 This driver adds support for the PolarFire SoC (MPFS) mailbox controller.
172 module will be called mailbox-mpfs.
181 providing an interface for invoking the inter-process communication
194 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
197 An implementation of the APM X-Gene Interprocessor Communication
198 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
199 It is used to send short messages between ARM64-bit cores and
201 want to use the APM X-Gene SLIMpro IPCM support.
227 with hardware for Inter-Processor Communication Controller (IPCC)
280 Qualcomm Technologies, Inc. Inter-Processor Communication Controller