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/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dmti,gic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPS Global Interrupt Controller
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
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/linux-5.10/drivers/clocksource/
Dmips-gic-timer.c6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 #define pr_fmt(fmt) "mips-gic-timer: " fmt
22 #include <asm/mips-cps.h>
59 int cpu = cpumask_first(evt->cpumask); in gic_next_event()
71 res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; in gic_next_event()
80 cd->event_handler(cd); in gic_compare_interrupt()
94 cd->name = "MIPS GIC"; in gic_clockevent_cpu_init()
95 cd->features = CLOCK_EVT_FEAT_ONESHOT | in gic_clockevent_cpu_init()
98 cd->rating = 350; in gic_clockevent_cpu_init()
99 cd->irq = gic_timer_irq; in gic_clockevent_cpu_init()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_TIMER_OF) += timer-of.o
3 obj-$(CONFIG_TIMER_PROBE) += timer-probe.o
4 obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o
5 obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o
6 obj-$(CONFIG_ATMEL_TCB_CLKSRC) += timer-atmel-tcb.o
7 obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
8 obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
9 obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += timer-cs5535.o
10 obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o
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/linux-5.10/arch/mips/mti-malta/
Dmalta-time.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Carsten Langgaard, carstenl@mips.com
4 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
6 * Setting up the clock on the MIPS boards.
28 #include <asm/mc146818-time.h>
30 #include <asm/mips-cps.h>
32 #include <asm/mips-boards/generic.h>
33 #include <asm/mips-boards/maltaint.h>
54 freq -= freq % (amount*2); in freqround()
59 * Estimate CPU and GIC frequencies.
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Dmalta-dtshim.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
15 #include <asm/mips-boards/generic.h>
16 #include <asm/mips-boards/malta.h>
17 #include <asm/mips-cps.h>
91 size -= size_preio; in gen_fdt_mem_array()
99 * obscures 256MB from 0x10000000-0x1fffffff. in gen_fdt_mem_array()
105 size -= SZ_256M; in gen_fdt_mem_array()
115 * obscures 256MB from 0x10000000-0x1fffffff in the low alias in gen_fdt_mem_array()
169 * SOC-it swaps, or perhaps doesn't swap, when DMA'ing in append_memory()
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/linux-5.10/drivers/irqchip/
Dirq-mips-gic.c6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
24 #include <asm/mips-cps.h>
28 #include <dt-bindings/interrupt-controller/mips-gic.h>
33 /* Add 2 to convert GIC CPU pin to core interrupt */
36 /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
39 /* Convert between local/shared IRQ number and GIC HW IRQ number. */
42 #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
45 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o
5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
11 obj-$(CONFIG_DAVINCI_AINTC) += irq-davinci-aintc.o
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/linux-5.10/arch/mips/boot/dts/img/
Dboston.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 stdout-path = "uart0:115200";
23 #address-cells = <1>;
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/linux-5.10/arch/mips/include/asm/
Dmips-gic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
16 /* The base address of the GIC registers */
19 /* Offsets from the GIC base address to various control blocks */
29 /* For read-only shared registers */
31 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
33 /* For read-write shared registers */
35 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
37 /* For read-only local registers */
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Dmips-cps.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
104 #include <asm/mips-cm.h>
105 #include <asm/mips-cpc.h>
106 #include <asm/mips-gic.h>
109 * mips_cps_numclusters - return the number of clusters present in the system
126 * mips_cps_cluster_config - return (GCR|CPC)_CONFIG from a cluster
160 * mips_cps_numcores - return the number of cores present in a cluster
176 * mips_cps_numiocu - return the number of IOCUs present in a cluster
195 * mips_cps_numvps - return the number of VPs (threads) supported by a core
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Dmips-cm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
20 /* The base address of the CM L2-only sync region */
24 * __mips_cm_phys_base - retrieve the physical base address of the CM
36 * mips_cm_is64 - determine CM register width
41 * or vice-versa. This variable indicates the width of the memory accesses
45 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
50 * mips_cm_error_report - Report CM cache errors
59 * mips_cm_probe - probe for a Coherence Manager
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/linux-5.10/arch/mips/boot/dts/mti/
Dsead3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
36 cpu_intc: interrupt-controller {
37 compatible = "mti,cpu-interrupt-controller";
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Dmalta.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/mips-gic.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 cpu_intc: interrupt-controller {
17 compatible = "mti,cpu-interrupt-controller";
19 interrupt-controller;
20 #interrupt-cells = <1>;
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/linux-5.10/drivers/staging/mt7621-dts/
Dmt7621.dtsi1 #include <dt-bindings/interrupt-controller/mips-gic.h>
2 #include <dt-bindings/gpio/gpio.h>
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mediatek,mt7621-soc";
11 compatible = "mips,mips1004Kc";
15 compatible = "mips,mips1004Kc";
20 #address-cells = <0>;
21 #interrupt-cells = <1>;
22 interrupt-controller;
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/linux-5.10/arch/mips/include/asm/mips-boards/
Dmaltaint.h6 * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved.
7 * Carsten Langgaard <carstenl@mips.com>
8 * Steven J. Hill <sjhill@mips.com>
23 #define MIPSCPU_INT_GIC MIPSCPU_INT_MB0 /* GIC chained interrupt */
33 * Interrupts 96..127 are used for Soc-it Classic interrupts
37 /* SOC-it Classic interrupt offsets */
42 * Interrupts 96..127 are used for Soc-it EIC interrupts
46 /* SOC-it EIC interrupt offsets */
Dmalta.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Carsten Langgaard, carstenl@mips.com
4 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
6 * Defines of the Malta board specific address-MAP, registers, etc.
13 #include <asm/mips-boards/msc01_pci.h>
16 /* Mips interrupt controller found in SOCit variations */
49 * GIC Specific definitions
71 * Malta RTC-device indirect register access.
/linux-5.10/arch/mips/kernel/
Dvdso.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <asm/mips-cps.h>
26 /* Kernel-provided data used by the VDSO. */
31 * Mapping for the VDSO data/GIC pages. The real pages are mapped manually, as
46 BUG_ON(!PAGE_ALIGNED(image->data)); in init_vdso_image()
47 BUG_ON(!PAGE_ALIGNED(image->size)); in init_vdso_image()
49 num_pages = image->size / PAGE_SIZE; in init_vdso_image()
51 data_pfn = __phys_to_pfn(__pa_symbol(image->data)); in init_vdso_image()
53 image->mapping.pages[i] = pfn_to_page(data_pfn + i); in init_vdso_image()
81 if (current->flags & PF_RANDOMIZE) { in vdso_base()
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Dsmp-cmp.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2007 MIPS Technologies, Inc.
5 * Chris Dearman (chris@mips.com)
34 /* Assume GIC is present */ in cmp_init_secondary()
38 /* Enable per-cpu interrupts: platform specific */ in cmp_init_secondary()
55 /* If we have an FPU, enroll ourselves in the FPU-full mask */ in cmp_smp_finish()
67 * (unsigned long)idle->thread_info the gp
100 /* If we have an FPU, enroll ourselves in the FPU-full mask */ in cmp_smp_setup()
132 * FIXME: some of these options are per-system, some per-core and in cmp_prepare_cpus()
133 * some per-cpu in cmp_prepare_cpus()
Dsmp-cps.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
17 #include <asm/mips-cps.h>
20 #include <asm/pm-cps.h>
22 #include <asm/smp-cps.h>
73 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { in cps_smp_setup()
112 /* If we have an FPU, enroll ourselves in the FPU-full mask */ in cps_smp_setup()
126 /* Detect whether the CCA is unsuited to multi-core SMP */ in cps_prepare_cpus()
131 /* The CCA is coherent, multi-core is fine */ in cps_prepare_cpus()
136 /* CCA is not coherent, multi-core is not usable */ in cps_prepare_cpus()
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/linux-5.10/arch/mips/generic/
Dboard-sead3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
17 #include <asm/yamon-dt.h>
56 /* leave the GIC node intact if a GIC is present */ in remove_gic()
61 gic_off = fdt_node_offset_by_compatible(fdt, -1, "mti,gic"); in remove_gic()
63 pr_err("unable to find DT GIC node: %d\n", gic_off); in remove_gic()
69 pr_err("unable to nop GIC node\n"); in remove_gic()
73 cpu_off = fdt_node_offset_by_compatible(fdt, -1, in remove_gic()
74 "mti,cpu-interrupt-controller"); in remove_gic()
83 return -EINVAL; in remove_gic()
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/linux-5.10/Documentation/devicetree/bindings/bus/
Dbaikal,bt1-axi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
23 accessible by means of the Baikal-T1 System Controller.
26 - $ref: /schemas/simple-bus.yaml#
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Dbaikal,bt1-apb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 APB-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect
15 which routes them to the AXI-APB bridge. This interface is a single master
22 - $ref: /schemas/simple-bus.yaml#
27 const: baikal,bt1-apb
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/linux-5.10/drivers/clk/imgtec/
Dclk-boston.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2016-2017 Imagination Technologies
4 * Author: Paul Burton <paul.burton@mips.com>
7 #define pr_fmt(fmt) "clk-boston: " fmt
9 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/boston-clock.h>
28 return (val & mask) >> (ffs(mask) - 1); in ext_field()
40 regmap = syscon_node_to_regmap(np->parent); in clk_boston_setup()
66 onecell->num = BOSTON_CLK_COUNT; in clk_boston_setup()
73 onecell->hws[BOSTON_CLK_INPUT] = hw; in clk_boston_setup()
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/linux-5.10/Documentation/devicetree/bindings/hwmon/
Dbaikal,bt1-pvt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/hwmon/baikal,bt1-pvt.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 PVT Sensor
11 - Serge Semin <fancer.lancer@gmail.com>
14 Baikal-T1 SoC provides an embedded process, voltage and temperature
17 which may cause the system instability and even damages. The IP-block
19 control wrapper, which provides a MMIO registers-based access to the
20 sensor core functionality (APB3-bus based) and exposes an additional
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/linux-5.10/Documentation/virt/kvm/
Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
13 - System ioctls: These query and set global attributes which affect the
17 - VM ioctls: These query and set attributes that affect an entire virtual
24 - vcpu ioctls: These query and set attributes that control the operation
32 - device ioctls: These query and set attributes that control the operation
80 facility that allows backward-compatible extensions to the API to be
104 the ioctl returns -ENOTTY.
122 -----------------------
139 -----------------
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