include/asm/mips-cm.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4  * Author: Paul Burton <paul.burton@mips.com>
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
20 /* The base address of the CM L2-only sync region */
24  * __mips_cm_phys_base - retrieve the physical base address of the CM
36  * mips_cm_is64 - determine CM register width
41  * or vice-versa. This variable indicates the width of the memory accesses
45  * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
50  * mips_cm_error_report - Report CM cache errors
59  * mips_cm_probe - probe for a Coherence Manager
62  * is successfully detected, else -errno.
69 	return -ENODEV;  in mips_cm_probe()
74  * mips_cm_present - determine whether a Coherence Manager is present
88  * mips_cm_has_l2sync - determine whether an L2-only sync region is present
90  * Returns true if the system implements an L2-only sync region, else false.
110 /* Size of the L2-only sync region */
129 /* GCR_CONFIG - Information about the system */
137 /* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
146 /* GCR_ACCESS - Controls core/IOCU access to GCRs */
150 /* GCR_REV - Indicates the Coherence Manager revision */
164 /* GCR_ERR_CONTROL - Control error checking logic */
169 /* GCR_ERR_MASK - Control which errors are reported as interrupts */
172 /* GCR_ERR_CAUSE - Indicates the type of error that occurred */
178 /* GCR_ERR_ADDR - Indicates the address associated with an error */
181 /* GCR_ERR_MULT - Indicates when multiple errors have occurred */
185 /* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
190 /* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
195 /* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
200 /* GCR_REGn_BASE - Base addresses of CM address regions */
207 /* GCR_REGn_MASK - Size & destination of CM address regions */
222 /* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
226 /* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
230 /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
237 /* GCR_SYS_CONFIG2 - Further information about the system */
241 /* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
247 /* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
252 /* GCR_L2SM_COP - L2 cache op state machine control */
274 /* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
279 /* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
282 /* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
285 /* GCR_Cx_COHERENCE - Controls core coherence */
290 /* GCR_Cx_CONFIG - Information about a core's configuration */
295 /* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
310 /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
314 /* GCR_Cx_ID - Identify the current core */
319 /* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
328  * mips_cm_l2sync - perform an L2-only sync operation
330  * If an L2-only sync region is present in the system then this function
331  * performs and L2-only sync and returns zero. Otherwise it returns -ENODEV.
336 		return -ENODEV;  in mips_cm_l2sync()
343  * mips_cm_revision() - return CM revision
357  * mips_cm_max_vp_width() - return the width in bits of VP indices
387  * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
390  * Hardware such as the GIC uses identifiers for VPs which may not match the
407  * mips_cm_lock_other - lock access to redirect/other region
420  * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
428  * mips_cm_unlock_other - unlock access to redirect/other region
444  * mips_cm_lock_other_cpu - lock access to redirect/other region