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/qemu/tests/tcg/s390x/
H A Dex-relative-long.c14 * Each test sets the MEM_IDXth element of the mem array to MEM and uses a
16 * This is in order to prevent stumbling upon MEM in random memory in case
20 * clang doesn't, so the assembly code accesses mem[MEM_IDX] using MEM_ASM.
22 static long mem[0x1000]; variable
24 #define MEM_ASM "mem+0x800*8"
29 /* Initial mem[MEM_IDX] value. */
30 #define MEM 0xfedcba9889abcdef macro
37 F(cgfrl, REG, MEM, 2) \
38 F(cghrl, REG, MEM, 2) \
39 F(cgrl, REG, MEM, 2) \
[all …]
/qemu/tests/tcg/x86_64/
H A Dcmpxchg.c3 static int mem; variable
8 mem = orig; in test_cmpxchgb()
9 asm("cmpxchgb %b[cmp],%[mem]" in test_cmpxchgb()
10 : [ mem ] "+m"(mem), [ rax ] "=a"(ret) in test_cmpxchgb()
18 mem = orig; in test_cmpxchgw()
19 asm("cmpxchgw %w[cmp],%[mem]" in test_cmpxchgw()
20 : [ mem ] "+m"(mem), [ rax ] "=a"(ret) in test_cmpxchgw()
28 mem = orig; in test_cmpxchgl()
29 asm("cmpxchgl %[cmp],%[mem]" in test_cmpxchgl()
30 : [ mem ] "+m"(mem), [ rax ] "=a"(ret) in test_cmpxchgl()
/qemu/pc-bios/dtb/
H A Dpetalogix-ml605.dts256 xlnx,max-mem-width = < 0x10 >;
265 xlnx,num-banks-mem = < 0x01 >;
266 xlnx,parity-type-mem-0 = < 0x00 >;
267 xlnx,parity-type-mem-1 = < 0x00 >;
268 xlnx,parity-type-mem-2 = < 0x00 >;
269 xlnx,parity-type-mem-3 = < 0x00 >;
271 xlnx,s-axi-mem-addr-width = < 0x20 >;
272 xlnx,s-axi-mem-data-width = < 0x20 >;
273 xlnx,s-axi-mem-id-width = < 0x01 >;
274 xlnx,s-axi-mem-protocol = "AXI4LITE";
[all …]
H A Dpetalogix-s3adsp1800.dts142 xlnx,max-mem-width = <0x08>;
162 xlnx,num-banks-mem = <0x01>;
165 xlnx,synch-mem-0 = <0x00>;
166 xlnx,synch-mem-1 = <0x00>;
167 xlnx,synch-mem-2 = <0x00>;
168 xlnx,synch-mem-3 = <0x00>;
173 xlnx,tavdv-ps-mem-0 = <0x11170>;
174 xlnx,tavdv-ps-mem-1 = <0x3a98>;
175 xlnx,tavdv-ps-mem-2 = <0x3a98>;
176 xlnx,tavdv-ps-mem-3 = <0x3a98>;
[all …]
/qemu/host/include/aarch64/host/
H A Datomic128-ldst.h.inc34 asm("ldp %[l], %[h], %[mem]"
35 : [l] "=r"(l), [h] "=r"(h) : [mem] "m"(*ptr));
47 asm("ldp %[l], %[h], %[mem]"
48 : [l] "=r"(l), [h] "=r"(h) : [mem] "m"(*ptr));
51 asm("0: ldxp %[l], %[h], %[mem]\n\t"
52 "stxp %w[tmp], %[l], %[h], %[mem]\n\t"
54 : [mem] "+m"(*ptr), [tmp] "=&r"(tmp), [l] "=&r"(l), [h] "=&r"(h));
67 asm("stp %[l], %[h], %[mem]"
68 : [mem] "=m"(*ptr) : [l] "r"(l), [h] "r"(h));
71 asm("0: ldxp %[t1], %[t2], %[mem]\n\t"
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/qemu/hw/vfio/
H A Dregion.c206 region->mem = g_new0(MemoryRegion, 1); in vfio_region_setup()
207 memory_region_init_io(region->mem, obj, &vfio_region_ops, in vfio_region_setup()
231 trace_vfio_region_unmap(memory_region_name(&region->mmaps[index].mem), in vfio_subregion_unmap()
235 memory_region_del_subregion(region->mem, &region->mmaps[index].mem); in vfio_subregion_unmap()
237 object_unparent(OBJECT(&region->mmaps[index].mem)); in vfio_subregion_unmap()
247 if (!region->mem) { in vfio_region_mmap()
296 memory_region_name(region->mem), i); in vfio_region_mmap()
297 memory_region_init_ram_device_ptr(&region->mmaps[i].mem, in vfio_region_mmap()
298 memory_region_owner(region->mem), in vfio_region_mmap()
302 memory_region_add_subregion(region->mem, region->mmaps[i].offset, in vfio_region_mmap()
[all …]
H A Dpci-quirks.c168 memory_region_name(mirror->mem), in vfio_generic_quirk_mirror_read()
182 memory_region_name(mirror->mem), in vfio_generic_quirk_mirror_write()
238 quirk->mem = g_new0(MemoryRegion, nr_mem); in vfio_quirk_alloc()
379 memory_region_init_io(quirk->mem, OBJECT(vdev), &vfio_ati_3c3_quirk, vdev, in vfio_vga_probe_ati_3c3_quirk()
381 memory_region_add_subregion(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem, in vfio_vga_probe_ati_3c3_quirk()
382 3 /* offset 3 bytes from 0x3c0 */, quirk->mem); in vfio_vga_probe_ati_3c3_quirk()
420 window->addr_mem = &quirk->mem[0]; in vfio_probe_ati_bar4_quirk()
421 window->data_mem = &quirk->mem[1]; in vfio_probe_ati_bar4_quirk()
426 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, in vfio_probe_ati_bar4_quirk()
433 memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, in vfio_probe_ati_bar4_quirk()
[all …]
/qemu/target/rx/
H A Dtranslate.c164 static inline void rx_gen_ld(unsigned int size, TCGv reg, TCGv mem) in rx_gen_ld() argument
166 tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE); in rx_gen_ld()
170 static inline void rx_gen_ldu(unsigned int size, TCGv reg, TCGv mem) in rx_gen_ldu() argument
172 tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE); in rx_gen_ldu()
176 static inline void rx_gen_st(unsigned int size, TCGv reg, TCGv mem) in rx_gen_st() argument
178 tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE); in rx_gen_st()
182 static inline void rx_gen_regindex(DisasContext *ctx, TCGv mem, in rx_gen_regindex() argument
185 tcg_gen_shli_i32(mem, cpu_regs[ri], size); in rx_gen_regindex()
186 tcg_gen_add_i32(mem, mem, cpu_regs[rb]); in rx_gen_regindex()
190 static inline TCGv rx_index_addr(DisasContext *ctx, TCGv mem, in rx_index_addr() argument
[all …]
/qemu/tests/qtest/
H A Dcxl-test.c38 "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
39 "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
43 "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
44 "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
53 "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
57 "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
58 "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
60 "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
61 "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \
65 "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
[all …]
/qemu/hw/pci-host/
H A Dpam.c33 void init_pam(PAMMemoryRegion *mem, Object *owner, MemoryRegion *ram_memory, in init_pam() argument
40 memory_region_init_alias(&mem->alias[3], owner, "pam-ram", ram_memory, in init_pam()
43 memory_region_init_alias(&mem->alias[1], owner, "pam-rom", ram_memory, in init_pam()
45 memory_region_set_readonly(&mem->alias[1], true); in init_pam()
48 memory_region_init_alias(&mem->alias[0], owner, "pam-pci", pci_address_space, in init_pam()
50 memory_region_init_alias(&mem->alias[2], owner, "pam-pci", ram_memory, in init_pam()
55 memory_region_set_enabled(&mem->alias[i], false); in init_pam()
57 &mem->alias[i], 1); in init_pam()
60 mem->current = 0; in init_pam()
H A Ddesignware.c120 MemoryRegion *mem = &root->msi.iomem; in designware_pcie_root_update_msi_mapping() local
124 memory_region_set_address(mem, base); in designware_pcie_root_update_msi_mapping()
125 memory_region_set_enabled(mem, enable); in designware_pcie_root_update_msi_mapping()
283 current = &viewport->mem; in designware_pcie_update_viewport()
288 other = &viewport->mem; in designware_pcie_update_viewport()
292 * An outbound viewport can be reconfigure from being MEM to CFG, in designware_pcie_update_viewport()
422 MemoryRegion *source, *destination, *mem; in designware_pcie_root_realize() local
441 mem = &viewport->mem; in designware_pcie_root_realize()
442 name = designware_pcie_viewport_name(direction, i, "MEM"); in designware_pcie_root_realize()
443 memory_region_init_alias(mem, OBJECT(root), name, destination, in designware_pcie_root_realize()
[all …]
H A Dppce500.c80 MemoryRegion mem; member
88 MemoryRegion mem; member
203 MemoryRegion *mem = &pci->pib[idx].mem; in e500_update_piw() local
207 if (memory_region_is_mapped(mem)) { in e500_update_piw()
209 memory_region_del_subregion(bm, mem); in e500_update_piw()
210 object_unparent(OBJECT(mem)); in e500_update_piw()
219 memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar, in e500_update_piw()
221 memory_region_add_subregion_overlap(bm, wbar, mem, -1); in e500_update_piw()
235 MemoryRegion *mem = &pci->pob[idx].mem; in e500_update_pow() local
239 if (memory_region_is_mapped(mem)) { in e500_update_pow()
[all …]
/qemu/target/arm/tcg/
H A Dmte_helper.c265 int load_tag1(uint64_t ptr, uint8_t *mem) in load_tag1() argument
268 return extract32(*mem, ofs, 4); in load_tag1()
274 uint8_t *mem; in HELPER() local
278 mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, 1, in HELPER()
282 if (mem) { in HELPER()
283 rtag = load_tag1(ptr, mem); in HELPER()
299 void store_tag1(uint64_t ptr, uint8_t *mem, int tag) in store_tag1() argument
302 *mem = deposit32(*mem, ofs, 4, tag); in store_tag1()
306 static void store_tag1_parallel(uint64_t ptr, uint8_t *mem, int tag) in store_tag1_parallel() argument
309 uint8_t old = qatomic_read(mem); in store_tag1_parallel()
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/qemu/docs/system/
H A Dvm-templating.rst49 -object memory-backend-file,id=pc.ram,mem-path=template,size=2g,share=on,... \\
73 -object memory-backend-file,id=pc.ram,mem-path=template,size=2g,readonly=on,rom=off,... \\
79 Note that ``-mem-path`` cannot be used for VM templating when creating the
105 virtio-mem
108 virtio-mem cannot discard VM RAM that is managed by the virtio-mem
109 device. virtio-mem will fail early when realizing the device. To use
110 VM templating with virtio-mem, either hotplug virtio-mem devices to the
111 new VM, or don't supply any memory to the template VM using virtio-mem
113 virtio-mem device.
/qemu/accel/kvm/
H A Dkvm-all.c142 static void kvm_slot_init_dirty_bitmap(KVMSlot *mem);
302 KVMSlot *mem = &kml->slots[i]; in kvm_lookup_matching_slot() local
304 if (start_addr == mem->start_addr && size == mem->memory_size) { in kvm_lookup_matching_slot()
305 return mem; in kvm_lookup_matching_slot()
344 KVMSlot *mem = &kml->slots[i]; in kvm_physical_memory_addr_from_host() local
346 if (ram >= mem->ram && ram < mem->ram + mem->memory_size) { in kvm_physical_memory_addr_from_host()
347 *phys_addr = mem->start_addr + (ram - mem->ram); in kvm_physical_memory_addr_from_host()
360 struct kvm_userspace_memory_region2 mem; in kvm_set_user_memory_region() local
363 mem.slot = slot->slot | (kml->as_id << 16); in kvm_set_user_memory_region()
364 mem.guest_phys_addr = slot->start_addr; in kvm_set_user_memory_region()
[all …]
/qemu/include/
H A Dglib-compat.h80 * @mem: (nullable): the memory to copy.
84 * from @mem. If @mem is %NULL it returns %NULL.
94 * or %NULL if @mem is %NULL.
96 static inline gpointer g_memdup2_qemu(gconstpointer mem, gsize byte_size) in g_memdup2_qemu() argument
99 return g_memdup2(mem, byte_size); in g_memdup2_qemu()
103 if (mem && byte_size != 0) { in g_memdup2_qemu()
105 memcpy(new_mem, mem, byte_size); in g_memdup2_qemu()
/qemu/accel/hvf/
H A Dhvf-accel-ops.c112 ret = hv_vm_map(slot->mem, slot->start, slot->size, flags); in do_hvf_set_memory()
119 hvf_slot *mem; in hvf_set_phys_mem() local
143 mem = hvf_find_overlap_slot( in hvf_set_phys_mem()
147 if (mem && add) { in hvf_set_phys_mem()
148 if (mem->size == int128_get64(section->size) && in hvf_set_phys_mem()
149 mem->start == section->offset_within_address_space && in hvf_set_phys_mem()
150 mem->mem == (memory_region_get_ram_ptr(area) + in hvf_set_phys_mem()
157 if (mem) { in hvf_set_phys_mem()
158 mem->size = 0; in hvf_set_phys_mem()
159 if (do_hvf_set_memory(mem, 0)) { in hvf_set_phys_mem()
[all …]
/qemu/scripts/
H A Ddisas-objdump.pl41 my $mem = "";
59 $mem = $mem . pack("H*", substr($_, 8, -1));
63 $mem = $mem . pack("H*", substr($_, 8, -1));
72 syswrite $outh, $mem;
89 $mem = "";
/qemu/hw/net/
H A Dne2000.c129 memcpy(s->mem, &s->c.macaddr, 6); in ne2000_reset()
130 s->mem[14] = 0x57; in ne2000_reset()
131 s->mem[15] = 0x57; in ne2000_reset()
135 s->mem[2 * i] = s->mem[i]; in ne2000_reset()
136 s->mem[2 * i + 1] = s->mem[i]; in ne2000_reset()
201 } else if (s->mem[0] == buf[0] && in ne2000_receive()
202 s->mem[2] == buf[1] && in ne2000_receive()
203 s->mem[4] == buf[2] && in ne2000_receive()
204 s->mem[6] == buf[3] && in ne2000_receive()
205 s->mem[8] == buf[4] && in ne2000_receive()
[all …]
/qemu/hw/virtio/
H A Dvirtio-mem-pci.h2 * Virtio MEM PCI device
17 #include "hw/virtio/virtio-mem.h"
23 * virtio-mem-pci: This extends VirtIOMDPCI.
25 #define TYPE_VIRTIO_MEM_PCI "virtio-mem-pci-base"
/qemu/hw/s390x/
H A Dvirtio-ccw-mem.h2 * Virtio MEM CCW device
17 #include "hw/virtio/virtio-mem.h"
23 * virtio-mem-ccw: This extends VirtIOMDCcw
25 #define TYPE_VIRTIO_MEM_CCW "virtio-mem-ccw"
/qemu/hw/display/
H A Dframebuffer.c76 MemoryRegion *mem; in framebuffer_update_display() local
81 mem = mem_section->mr; in framebuffer_update_display()
82 if (!mem) { in framebuffer_update_display()
87 src = memory_region_get_ram_ptr(mem) + addr; in framebuffer_update_display()
102 snap = memory_region_snapshot_and_clear_dirty(mem, addr, src_width * rows, in framebuffer_update_display()
105 dirty = memory_region_snapshot_get_dirty(mem, snap, addr, src_width); in framebuffer_update_display()
/qemu/qapi/
H A Dcxl.json235 # @mem-data-parity: Data error such as data parity or data ECC error
236 # on CXL.mem
238 # @mem-address-parity: Address parity or other errors associated with
239 # the address field on CXL.mem
241 # @mem-be-parity: Byte enable parity or other byte enable errors on
242 # CXL.mem.
244 # @mem-data-ecc: Data ECC error on CXL.mem.
269 'mem-data-parity',
270 'mem-address-parity',
271 'mem-be-parity',
[all …]
/qemu/include/standard-headers/linux/
H A Dvirtio_mem.h3 * Virtio Mem Device
47 * Each virtio-mem device manages a dedicated region in physical address
49 * for a single NUMA node are possible. A virtio-mem device is like a
54 * Virtio-mem devices can only operate on their assigned memory region in
87 /* --- virtio-mem: feature bits --- */
97 /* --- virtio-mem: guest -> host requests --- */
138 /* --- virtio-mem: host -> guest response --- */
189 /* --- virtio-mem: configuration --- */
/qemu/hw/core/
H A Dmachine.c32 #include "hw/mem/nvdimm.h"
50 { "virtio-mem-pci", "vectors", "0" },
99 { "virtio-mem", "x-early-migration", "false" },
598 MemorySizeConfiguration mem = { in machine_get_mem() local
606 MemorySizeConfiguration *p_mem = &mem; in machine_get_mem()
617 MemorySizeConfiguration *mem; in machine_set_mem() local
619 if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) { in machine_set_mem()
623 if (!mem->has_size) { in machine_set_mem()
624 mem->has_size = true; in machine_set_mem()
625 mem->size = mc->default_ram_size; in machine_set_mem()
[all …]

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