/qemu/tests/tcg/i386/ |
H A D | test-i386-bmi2.c | 45 insn2q(pext, src, "r", mask, "rm") 46 insn2q(pdep, src, "r", mask, "rm") 58 insn2l(pext, src, "r", mask, "rm") in insn1q() 59 insn2l(pdep, src, "r", mask, "rm") in insn1q() 73 uint64_t mask = 0xa080800302020001ull; in insn1q() local 78 result = andnq(mask, ehlo); in insn1q() 81 result = pextq(ehlo, mask); in insn1q() 84 result = pdepq(result, mask); in insn1q() 85 assert(result == (ehlo & mask)); in insn1q() 87 result = pextq(-1ull, mask); in insn1q() [all …]
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/qemu/target/arm/tcg/ |
H A D | mve_helper.c | 33 * Return the mask of which elements in the MVE vector correspond in mve_eci_mask() 34 * to beats being executed. The mask has 1 bits for executed lanes in mve_eci_mask() 62 * Return the mask of which elements in the MVE vector should be in mve_element_mask() 66 * (3) low-overhead-branch tail predication will mask out part in mve_element_mask() 71 * as VPR.P0: 0 to mask the lane, 1 if it is active. in mve_element_mask() 76 * the 4-bit slice of the mask corresponding to a single beat. in mve_element_mask() 78 uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); in mve_element_mask() local 81 mask |= 0xff; in mve_element_mask() 84 mask |= 0xff00; in mve_element_mask() 98 mask &= ltpmask; in mve_element_mask() [all …]
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/qemu/target/mips/tcg/system/ |
H A D | cp0_helper.c | 160 uint32_t mask = ((1U << CP0St_CU3) in sync_c0_tcstatus() local 176 cpu->CP0_Status &= ~mask; in sync_c0_tcstatus() 517 uint32_t mask = 0; in helper_mtc0_mvpcontrol() local 521 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | in helper_mtc0_mvpcontrol() 525 mask |= (1 << CP0MVPCo_STLB); in helper_mtc0_mvpcontrol() 527 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); in helper_mtc0_mvpcontrol() 536 uint32_t mask; in helper_mtc0_vpecontrol() local 539 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | in helper_mtc0_vpecontrol() 541 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); in helper_mtc0_vpecontrol() 557 uint32_t mask; in helper_mttc0_vpecontrol() local [all …]
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/qemu/hw/intc/ |
H A D | loongarch_pch_pic.c | 16 static void pch_pic_update_irq(LoongArchPICCommonState *s, uint64_t mask, in pch_pic_update_irq() argument 23 val = mask & s->intirr & ~s->int_mask; in pch_pic_update_irq() 34 val = mask & s->intisr & ~s->intirr; in pch_pic_update_irq() 46 uint64_t mask = 1ULL << irq; in pch_pic_irq_handler() local 51 if (s->intedge & mask) { in pch_pic_irq_handler() 54 if ((s->last_intirr & mask) == 0) { in pch_pic_irq_handler() 56 s->intirr |= mask; in pch_pic_irq_handler() 58 s->last_intirr |= mask; in pch_pic_irq_handler() 60 s->last_intirr &= ~mask; in pch_pic_irq_handler() 65 s->intirr |= mask; in pch_pic_irq_handler() [all …]
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H A D | i8259.c | 58 /* return the highest priority found in mask (highest = smallest 60 static int get_priority(PICCommonState *s, int mask) in get_priority() argument 64 if (mask == 0) { in get_priority() 68 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) { in get_priority() 77 int mask, cur_priority, priority; in pic_get_irq() local 79 mask = s->irr & ~s->imr; in pic_get_irq() 80 priority = get_priority(s, mask); in pic_get_irq() 87 mask = s->isr; in pic_get_irq() 89 mask &= ~s->imr; in pic_get_irq() 92 mask &= ~(1 << 2); in pic_get_irq() [all …]
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/qemu/hw/net/rocker/ |
H A D | rocker-hmp-cmds.c | 80 monitor_printf(mon, "prio tbl hits key(mask) --> actions\n"); in hmp_rocker_of_dpa_flows() 85 RockerOfDpaFlowMask *mask = flow->mask; in hmp_rocker_of_dpa_flows() local 98 if (mask->has_in_pport) { in hmp_rocker_of_dpa_flows() 99 monitor_printf(mon, "(0x%x)", mask->in_pport); in hmp_rocker_of_dpa_flows() 106 if (mask->has_vlan_id) { in hmp_rocker_of_dpa_flows() 107 monitor_printf(mon, "(0x%x)", mask->vlan_id); in hmp_rocker_of_dpa_flows() 113 if (mask->has_tunnel_id) { in hmp_rocker_of_dpa_flows() 114 monitor_printf(mon, "(0x%x)", mask->tunnel_id); in hmp_rocker_of_dpa_flows() 143 mask->eth_src && in hmp_rocker_of_dpa_flows() 144 (strcmp(mask->eth_src, "01:00:00:00:00:00") == 0)) { in hmp_rocker_of_dpa_flows() [all …]
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H A D | rocker_of_dpa.c | 132 OfDpaFlowKey mask; member 199 static int of_dpa_mask2prefix(uint32_t mask) in of_dpa_mask2prefix() argument 205 if (!(ntohl(mask) & ((2 << i) - 1))) { in of_dpa_mask2prefix() 214 static void of_dpa_flow_key_dump(OfDpaFlowKey *key, OfDpaFlowKey *mask) in of_dpa_flow_key_dump() argument 220 if (key->in_pport || (mask && mask->in_pport)) { in of_dpa_flow_key_dump() 222 if (mask && mask->in_pport != 0xffffffff) { in of_dpa_flow_key_dump() 227 if (key->tunnel_id || (mask && mask->tunnel_id)) { in of_dpa_flow_key_dump() 229 if (mask && mask->tunnel_id != 0xffffffff) { in of_dpa_flow_key_dump() 234 if (key->eth.vlan_id || (mask && mask->eth.vlan_id)) { in of_dpa_flow_key_dump() 236 if (mask && mask->eth.vlan_id != 0xffff) { in of_dpa_flow_key_dump() [all …]
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/qemu/target/s390x/tcg/ |
H A D | cc_helper.c | 89 static uint32_t cc_calc_tm_32(uint32_t val, uint32_t mask) in cc_calc_tm_32() argument 91 uint32_t r = val & mask; in cc_calc_tm_32() 95 } else if (r == mask) { in cc_calc_tm_32() 102 static uint32_t cc_calc_tm_64(uint64_t val, uint64_t mask) in cc_calc_tm_64() argument 104 uint64_t r = val & mask; in cc_calc_tm_64() 108 } else if (r == mask) { in cc_calc_tm_64() 111 int top = clz64(mask); in cc_calc_tm_64() 255 /* calculate condition code for insert character under mask insn */ 256 static uint32_t cc_calc_icm(uint64_t mask, uint64_t val) in cc_calc_icm() argument 258 if ((val & mask) == 0) { in cc_calc_icm() [all …]
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H A D | vec_string_helper.c | 22 * as defined by the mask. 24 static inline uint64_t zero_search(uint64_t a, uint64_t mask) in zero_search() argument 26 return ~(((a & mask) + mask) | a | mask); in zero_search() 31 * as defined by the mask. 33 static inline uint64_t nonzero_search(uint64_t a, uint64_t mask) in nonzero_search() argument 35 return (((a & mask) + mask) | a) & ~mask; in nonzero_search() 81 const uint64_t mask = get_element_lsbs_mask(es); in vfae() local 98 e0 |= zero_search(a0 ^ t0, mask); in vfae() 99 e0 |= zero_search(a0 ^ t1, mask); in vfae() 100 e1 |= zero_search(a1 ^ t0, mask); in vfae() [all …]
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H A D | excp_helper.c | 161 if (!(env->psw.mask & PSW_MASK_64)) { in s390_cpu_tlb_fill() 167 if (!(env->psw.mask & PSW_MASK_64)) { in s390_cpu_tlb_fill() 203 uint64_t mask, addr; in do_program_interrupt() local 262 __func__, env->int_pgm_code, ilen, env->psw.mask, in do_program_interrupt() 281 lowcore->program_old_psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(env)); in do_program_interrupt() 283 mask = be64_to_cpu(lowcore->program_new_psw.mask); in do_program_interrupt() 289 s390_cpu_set_psw(env, mask, addr); in do_program_interrupt() 294 uint64_t mask, addr; in do_svc_interrupt() local 301 lowcore->svc_old_psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(env)); in do_svc_interrupt() 303 mask = be64_to_cpu(lowcore->svc_new_psw.mask); in do_svc_interrupt() [all …]
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/qemu/target/mips/system/ |
H A D | cp0.c | 32 uint32_t mask = ((1 << CP0TCSt_TCU3) in sync_c0_status() local 56 *tcst &= ~mask; in sync_c0_status() 63 uint32_t mask = env->CP0_Status_rw_bitmask; in cpu_mips_store_status() local 67 bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; in cpu_mips_store_status() 75 mask &= ~(3 << CP0St_KSU); in cpu_mips_store_status() 77 mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); in cpu_mips_store_status() 80 env->CP0_Status = (old & ~mask) | (val & mask); in cpu_mips_store_status() 96 uint32_t mask = 0x00C00300; in cpu_mips_store_cause() local 101 mask |= 1 << CP0Ca_DC; in cpu_mips_store_cause() 104 mask &= ~((1 << CP0Ca_WP) & val); in cpu_mips_store_cause() [all …]
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/qemu/include/hw/pci/ |
H A D | pci.h | 304 void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask); 305 void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask); 860 * helper functions to do bit mask operation on configuration space. 866 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask) in pci_byte_test_and_clear_mask() argument 869 pci_set_byte(config, val & ~mask); in pci_byte_test_and_clear_mask() 870 return val & mask; in pci_byte_test_and_clear_mask() 874 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask) in pci_byte_test_and_set_mask() argument 877 pci_set_byte(config, val | mask); in pci_byte_test_and_set_mask() 878 return val & mask; in pci_byte_test_and_set_mask() 882 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask) in pci_word_test_and_clear_mask() argument [all …]
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/qemu/include/qemu/ |
H A D | log.h | 49 /* log only if a bit is set on the current loglevel mask: 50 * @mask: bit to check in the mask 54 #define qemu_log_mask(MASK, FMT, ...) \ argument 56 if (unlikely(qemu_loglevel_mask(MASK))) { \ 61 /* log only if a bit is set on the current loglevel mask 63 * @mask: bit to check in the mask 68 #define qemu_log_mask_and_addr(MASK, ADDR, FMT, ...) \ argument 70 if (unlikely(qemu_loglevel_mask(MASK)) && \ 80 int mask; member
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H A D | bitops.h | 69 unsigned long mask = BIT_MASK(nr); in set_bit() local 72 *p |= mask; in set_bit() 82 unsigned long mask = BIT_MASK(nr); in set_bit_atomic() local 85 qatomic_or(p, mask); in set_bit_atomic() 95 unsigned long mask = BIT_MASK(nr); in clear_bit() local 98 *p &= ~mask; in clear_bit() 108 unsigned long mask = BIT_MASK(nr); in clear_bit_atomic() local 111 return qatomic_and(p, ~mask); in clear_bit_atomic() 121 unsigned long mask = BIT_MASK(nr); in change_bit() local 124 *p ^= mask; in change_bit() [all …]
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/qemu/util/ |
H A D | compatfd.c | 24 sigset_t mask; member 36 err = sigwait(&info->mask, &sig); in sigwait_compat() 55 static int qemu_signalfd_compat(const sigset_t *mask) in qemu_signalfd_compat() argument 68 memcpy(&info->mask, mask, sizeof(*mask)); in qemu_signalfd_compat() 77 int qemu_signalfd(const sigset_t *mask) in qemu_signalfd() argument 82 ret = signalfd(-1, mask, SFD_CLOEXEC); in qemu_signalfd() 88 return qemu_signalfd_compat(mask); in qemu_signalfd()
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/qemu/hw/gpio/ |
H A D | mpc8xxx.c | 85 case 0x10: /* Interrupt Mask */ in mpc8xxx_gpio_read() 101 uint32_t mask = 0x80000000 >> i; in mpc8xxx_write_data() local 102 if (!(diff & mask)) { in mpc8xxx_write_data() 106 if (s->dir & mask) { in mpc8xxx_write_data() 108 qemu_set_irq(s->out[i], (new_data & mask) != 0); in mpc8xxx_write_data() 138 case 0x10: /* Interrupt Mask */ in mpc8xxx_gpio_write() 164 uint32_t mask; in mpc8xxx_gpio_set_irq() local 166 mask = 0x80000000 >> irq; in mpc8xxx_gpio_set_irq() 167 if ((s->dir & mask) == 0) { in mpc8xxx_gpio_set_irq() 168 uint32_t old_value = s->dat & mask; in mpc8xxx_gpio_set_irq() [all …]
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H A D | pl061.c | 119 * Return mask of bits which correspond to pins configured as inputs in pl061_floating() 139 * Return mask of bits which correspond to pins configured as inputs in pl061_pullups() 160 uint8_t mask; in pl061_update() local 180 mask = 1 << i; in pl061_update() 181 if (changed & mask) { in pl061_update() 182 int level = (out & mask) != 0; in pl061_update() 194 mask = 1 << i; in pl061_update() 195 if (changed & mask) { in pl061_update() 197 (s->data & mask) != 0); in pl061_update() 199 if (!(s->isense & mask)) { in pl061_update() [all …]
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/qemu/target/xtensa/ |
H A D | dbg_helper.c | 89 uint32_t mask = dbreakc | ~DBREAKC_MASK; in set_dbreak() local 100 /* contiguous mask after inversion is one less than some power of 2 */ in set_dbreak() 101 if ((~mask + 1) & ~mask) { in set_dbreak() 103 "DBREAKC mask is not contiguous: 0x%08x\n", dbreakc); in set_dbreak() 104 /* cut mask after the first zero bit */ in set_dbreak() 105 mask = 0xffffffff << (32 - clo32(mask)); in set_dbreak() 107 if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1, in set_dbreak() 112 dbreaka & mask, ~mask + 1); in set_dbreak()
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/qemu/crypto/ |
H A D | clmul.c | 16 uint64_t mask = (n & 0x0101010101010101ull) * 0xff; in clmul_8x8_low() local 17 r ^= m & mask; in clmul_8x8_low() 29 uint64_t mask = (n & 0x0001000100010001ull) * 0xffff; in clmul_8x4_even_int() local 30 r ^= m & mask; in clmul_8x4_even_int() 70 uint64_t mask = (n & 0x0000000100000001ull) * 0xffffffffull; in clmul_16x2_even() local 71 r ^= m & mask; in clmul_16x2_even() 106 uint64_t mask = -((n >> i) & 1); in clmul_64_gen() local 107 rl ^= (m << i) & mask; in clmul_64_gen() 108 rh ^= (m >> (64 - i)) & mask; in clmul_64_gen()
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/qemu/rust/qemu-api/src/ |
H A D | bitops.rs | 47 fn mask(start: u32, length: u32) -> Self in mask() method 63 let mask = Self::mask(start, length); in deposit() localVariable 64 (self & !mask) | ((Self::from(fieldval) << start) & mask) in deposit() 71 let mask = Self::mask(start, length); in extract() localVariable 72 (self & mask) >> start in extract() 116 assert_eq!(u8::mask(7, 1), 128); in test_mask() 117 assert_eq!(u32::mask(8, 8), 0xff00); in test_mask()
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/qemu/target/alpha/ |
H A D | int_helper.c | 28 uint64_t mask; in helper_zapnot() local 30 mask = -(mskb & 0x01) & 0x00000000000000ffull; in helper_zapnot() 31 mask |= -(mskb & 0x02) & 0x000000000000ff00ull; in helper_zapnot() 32 mask |= -(mskb & 0x04) & 0x0000000000ff0000ull; in helper_zapnot() 33 mask |= -(mskb & 0x08) & 0x00000000ff000000ull; in helper_zapnot() 34 mask |= -(mskb & 0x10) & 0x000000ff00000000ull; in helper_zapnot() 35 mask |= -(mskb & 0x20) & 0x0000ff0000000000ull; in helper_zapnot() 36 mask |= -(mskb & 0x40) & 0x00ff000000000000ull; in helper_zapnot() 37 mask |= -(mskb & 0x80) & 0xff00000000000000ull; in helper_zapnot() 39 return val & mask; in helper_zapnot() [all …]
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/qemu/hw/riscv/ |
H A D | riscv-iommu-hpm.c | 151 uint32_t mask = ~0; in riscv_iommu_hpm_incr_ctr() local 155 * 1001 1011 mask = GSCID in riscv_iommu_hpm_incr_ctr() 156 * 0000 0111 mask = mask ^ (mask + 1) in riscv_iommu_hpm_incr_ctr() 157 * 1111 1000 mask = ~mask; in riscv_iommu_hpm_incr_ctr() 159 mask = get_field(evt, RISCV_IOMMU_IOHPMEVT_DID_GSCID); in riscv_iommu_hpm_incr_ctr() 160 mask = mask ^ (mask + 1); in riscv_iommu_hpm_incr_ctr() 161 mask = ~mask; in riscv_iommu_hpm_incr_ctr() 164 if ((get_field(evt, RISCV_IOMMU_IOHPMEVT_DID_GSCID) & mask) != in riscv_iommu_hpm_incr_ctr() 165 (did_gscid & mask)) { in riscv_iommu_hpm_incr_ctr() 340 /* Update the counter mask if the event is already enabled. */ in update_event_map()
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/qemu/linux-user/s390x/ |
H A D | signal.c | 129 * Copy a 'clean' PSW mask to the user to avoid leaking in save_sigregs() 134 __put_user(psw_mask, &sregs->regs.psw.mask); in save_sigregs() 222 env->psw.mask = PSW_MASK_64 | PSW_MASK_32 | PSW_ASC_PRIMARY in setup_frame() 223 | (env->psw.mask & ~PSW_MASK_ASC); in setup_frame() 288 env->psw.mask = PSW_MASK_64 | PSW_MASK_32 | PSW_ASC_PRIMARY in setup_rt_frame() 289 | (env->psw.mask & ~PSW_MASK_ASC); in setup_rt_frame() 300 uint64_t prev_addr, prev_mask, mask, addr; in restore_sigregs() local 308 __get_user(mask, &sc->regs.psw.mask); in restore_sigregs() 313 * Use current psw.mask to preserve PER bit. in restore_sigregs() 315 * if (!is_ri_task(current) && (user_sregs.regs.psw.mask & PSW_MASK_RI)) in restore_sigregs() [all …]
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/qemu/ui/ |
H A D | cursor.c | 133 int transparent, uint8_t *mask) in cursor_set_mono() argument 138 bool expand_bitmap_only = image == mask; in cursor_set_mono() 143 * Converts a monochrome bitmap with XOR mask 'image' and AND mask 'mask': in cursor_set_mono() 150 if (transparent && mask[x/8] & bit) { in cursor_set_mono() 157 } else if (!transparent && !(mask[x/8] & bit)) { in cursor_set_mono() 169 mask += bpl; in cursor_set_mono() 200 void cursor_get_mono_mask(QEMUCursor *c, int transparent, uint8_t *mask) in cursor_get_mono_mask() argument 207 memset(mask, 0, bpl * c->height); in cursor_get_mono_mask() 213 mask[x/8] |= bit; in cursor_get_mono_mask() 217 mask[x/8] |= bit; in cursor_get_mono_mask() [all …]
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/qemu/target/loongarch/tcg/insn_trans/ |
H A D | trans_bit.c.inc | 116 TCGv mask = tcg_constant_tl(0x00FF00FF); 121 tcg_gen_and_tl(t0, t0, mask); 122 tcg_gen_and_tl(t1, src1, mask); 129 TCGv mask = tcg_constant_tl(0x00FF00FF00FF00FFULL); 134 tcg_gen_and_tl(t0, t0, mask); 135 tcg_gen_and_tl(t1, src1, mask); 144 TCGv_i64 mask = tcg_constant_i64(0x0000ffff0000ffffull); 147 tcg_gen_and_i64(t1, src1, mask); 148 tcg_gen_and_i64(t0, t0, mask); 157 TCGv mask = tcg_constant_tl(0x0000FFFF0000FFFFULL); [all …]
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