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/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dintel,lgm-io.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rahul.tanwar@linux.intel.com>
18 const: intel,lgm-io
25 '-pins$':
30 $ref: pinmux-node.yaml#
37 bias-pull-up: true
38 bias-pull-down: true
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/linux-5.10/drivers/pci/controller/dwc/
Dpcie-intel-gw.c1 // SPDX-License-Identifier: GPL-2.0
18 #include "pcie-designware.h"
20 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
88 return readl(lpp->app_base + ofs); in pcie_app_rd()
93 writel(val, lpp->app_base + ofs); in pcie_app_wr()
99 pcie_update_bits(lpp->app_base, ofs, mask, val); in pcie_app_wr_mask()
104 return dw_pcie_readl_dbi(&lpp->pci, ofs); in pcie_rc_cfg_rd()
109 dw_pcie_writel_dbi(&lpp->pci, ofs, val); in pcie_rc_cfg_wr()
115 pcie_update_bits(lpp->pci.dbi_base, ofs, mask, val); in pcie_rc_cfg_wr_mask()
132 u8 offset = dw_pcie_find_capability(&lpp->pci, PCI_CAP_ID_EXP); in intel_pcie_link_setup()
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/linux-5.10/drivers/pinctrl/
Dpinctrl-equilibrium.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pinctrl/pinconf-generic.h>
18 #include "pinctrl-equilibrium.h"
20 #define PIN_NAME_FMT "io-%d"
31 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
32 writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR); in eqbr_gpio_disable_irq()
33 raw_spin_unlock_irqrestore(&gctrl->lock, flags); in eqbr_gpio_disable_irq()
43 gc->direction_input(gc, offset); in eqbr_gpio_enable_irq()
44 raw_spin_lock_irqsave(&gctrl->lock, flags); in eqbr_gpio_enable_irq()
45 writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET); in eqbr_gpio_enable_irq()
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/linux-5.10/drivers/tty/serial/
Dlantiq.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/io.h>
150 spin_lock_irqsave(&ltq_port->lock, flags); in lqasc_start_tx()
152 spin_unlock_irqrestore(&ltq_port->lock, flags); in lqasc_start_tx()
159 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); in lqasc_stop_rx()
165 struct tty_port *tport = &port->state->port; in lqasc_rx_chars()
168 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & in lqasc_rx_chars()
170 while (fifocnt--) { in lqasc_rx_chars()
172 ch = readb(port->membase + LTQ_ASC_RBUF); in lqasc_rx_chars()
173 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) in lqasc_rx_chars()
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/linux-5.10/drivers/spi/
Dspi-lantiq-ssc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
11 #include <linux/io.h>
141 #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
190 return __raw_readl(spi->regbase + reg); in lantiq_ssc_readl()
196 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_writel()
202 u32 val = __raw_readl(spi->regbase + reg); in lantiq_ssc_maskl()
206 __raw_writel(val, spi->regbase + reg); in lantiq_ssc_maskl()
211 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg; in tx_fifo_level()
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