1 // SPDX-License-Identifier: GPL-2.0
18 #include "pcie-designware.h"
20 #define PORT_AFR_N_FTS_GEN12_DFT	(SZ_128 - 1)
88 	return readl(lpp->app_base + ofs);  in pcie_app_rd()
93 	writel(val, lpp->app_base + ofs);  in pcie_app_wr()
99 	pcie_update_bits(lpp->app_base, ofs, mask, val);  in pcie_app_wr_mask()
104 	return dw_pcie_readl_dbi(&lpp->pci, ofs);  in pcie_rc_cfg_rd()
109 	dw_pcie_writel_dbi(&lpp->pci, ofs, val);  in pcie_rc_cfg_wr()
115 	pcie_update_bits(lpp->pci.dbi_base, ofs, mask, val);  in pcie_rc_cfg_wr_mask()
132 	u8 offset = dw_pcie_find_capability(&lpp->pci, PCI_CAP_ID_EXP);  in intel_pcie_link_setup()
142 	switch (pci->link_gen) {  in intel_pcie_init_n_fts()
144 		pci->n_fts[1] = PORT_AFR_N_FTS_GEN3;  in intel_pcie_init_n_fts()
147 		pci->n_fts[1] = PORT_AFR_N_FTS_GEN4;  in intel_pcie_init_n_fts()
150 		pci->n_fts[1] = PORT_AFR_N_FTS_GEN12_DFT;  in intel_pcie_init_n_fts()
153 	pci->n_fts[0] = PORT_AFR_N_FTS_GEN12_DFT;  in intel_pcie_init_n_fts()
160 	intel_pcie_init_n_fts(&lpp->pci);  in intel_pcie_rc_setup()
161 	dw_pcie_setup_rc(&lpp->pci.pp);  in intel_pcie_rc_setup()
162 	dw_pcie_upconfig_setup(&lpp->pci);  in intel_pcie_rc_setup()
167 	struct device *dev = lpp->pci.dev;  in intel_pcie_ep_rst_init()
170 	lpp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);  in intel_pcie_ep_rst_init()
171 	if (IS_ERR(lpp->reset_gpio)) {  in intel_pcie_ep_rst_init()
172 		ret = PTR_ERR(lpp->reset_gpio);  in intel_pcie_ep_rst_init()
173 		if (ret != -EPROBE_DEFER)  in intel_pcie_ep_rst_init()
186 	reset_control_assert(lpp->core_rst);  in intel_pcie_core_rst_assert()
192 	 * One micro-second delay to make sure the reset pulse  in intel_pcie_core_rst_deassert()
196 	reset_control_deassert(lpp->core_rst);  in intel_pcie_core_rst_deassert()
207 	gpiod_set_value_cansleep(lpp->reset_gpio, 1);  in intel_pcie_device_rst_assert()
212 	msleep(lpp->rst_intrvl);  in intel_pcie_device_rst_deassert()
213 	gpiod_set_value_cansleep(lpp->reset_gpio, 0);  in intel_pcie_device_rst_deassert()
221 	return dw_pcie_wait_for_link(&lpp->pci);  in intel_pcie_app_logic_setup()
233 	struct dw_pcie *pci = &lpp->pci;  in intel_pcie_get_resources()
234 	struct device *dev = pci->dev;  in intel_pcie_get_resources()
237 	pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi");  in intel_pcie_get_resources()
238 	if (IS_ERR(pci->dbi_base))  in intel_pcie_get_resources()
239 		return PTR_ERR(pci->dbi_base);  in intel_pcie_get_resources()
241 	lpp->core_clk = devm_clk_get(dev, NULL);  in intel_pcie_get_resources()
242 	if (IS_ERR(lpp->core_clk)) {  in intel_pcie_get_resources()
243 		ret = PTR_ERR(lpp->core_clk);  in intel_pcie_get_resources()
244 		if (ret != -EPROBE_DEFER)  in intel_pcie_get_resources()
249 	lpp->core_rst = devm_reset_control_get(dev, NULL);  in intel_pcie_get_resources()
250 	if (IS_ERR(lpp->core_rst)) {  in intel_pcie_get_resources()
251 		ret = PTR_ERR(lpp->core_rst);  in intel_pcie_get_resources()
252 		if (ret != -EPROBE_DEFER)  in intel_pcie_get_resources()
257 	ret = device_property_read_u32(dev, "reset-assert-ms",  in intel_pcie_get_resources()
258 				       &lpp->rst_intrvl);  in intel_pcie_get_resources()
260 		lpp->rst_intrvl = RESET_INTERVAL_MS;  in intel_pcie_get_resources()
262 	lpp->app_base = devm_platform_ioremap_resource_byname(pdev, "app");  in intel_pcie_get_resources()
263 	if (IS_ERR(lpp->app_base))  in intel_pcie_get_resources()
264 		return PTR_ERR(lpp->app_base);  in intel_pcie_get_resources()
266 	lpp->phy = devm_phy_get(dev, "pcie");  in intel_pcie_get_resources()
267 	if (IS_ERR(lpp->phy)) {  in intel_pcie_get_resources()
268 		ret = PTR_ERR(lpp->phy);  in intel_pcie_get_resources()
269 		if (ret != -EPROBE_DEFER)  in intel_pcie_get_resources()
270 			dev_err(dev, "Couldn't get pcie-phy: %d\n", ret);  in intel_pcie_get_resources()
279 	phy_exit(lpp->phy);  in intel_pcie_deinit_phy()
286 	struct dw_pcie *pci = &lpp->pci;  in intel_pcie_wait_l2()
288 	if (pci->link_gen < 3)  in intel_pcie_wait_l2()
296 	ret = readl_poll_timeout(lpp->app_base + PCIE_APP_PMC, value,  in intel_pcie_wait_l2()
300 		dev_err(lpp->pci.dev, "PCIe link enter L2 timeout!\n");  in intel_pcie_wait_l2()
307 	if (dw_pcie_link_up(&lpp->pci))  in intel_pcie_turn_off()
322 	ret = phy_init(lpp->phy);  in intel_pcie_host_setup()
328 	ret = clk_prepare_enable(lpp->core_clk);  in intel_pcie_host_setup()
330 		dev_err(lpp->pci.dev, "Core clock enable failed: %d\n", ret);  in intel_pcie_host_setup()
346 	clk_disable_unprepare(lpp->core_clk);  in intel_pcie_host_setup()
358 	clk_disable_unprepare(lpp->core_clk);  in __intel_pcie_remove()
366 	struct pcie_port *pp = &lpp->pci.pp;  in intel_pcie_remove()
385 	clk_disable_unprepare(lpp->core_clk);  in intel_pcie_suspend_noirq()
399 	struct intel_pcie_port *lpp = dev_get_drvdata(pci->dev);  in intel_pcie_rc_init()
435 	struct device *dev = &pdev->dev;  in intel_pcie_probe()
443 		return -ENOMEM;  in intel_pcie_probe()
446 	pci = &lpp->pci;  in intel_pcie_probe()
447 	pci->dev = dev;  in intel_pcie_probe()
448 	pp = &pci->pp;  in intel_pcie_probe()
460 		return -ENODEV;  in intel_pcie_probe()
462 	pci->ops = &intel_pcie_ops;  in intel_pcie_probe()
463 	pci->version = data->pcie_ver;  in intel_pcie_probe()
464 	pci->atu_base = pci->dbi_base + data->pcie_atu_offset;  in intel_pcie_probe()
465 	pp->ops = &intel_pcie_dw_ops;  in intel_pcie_probe()
474 	 * Intel PCIe doesn't configure IO region, so set viewport  in intel_pcie_probe()
475 	 * to not perform IO region access.  in intel_pcie_probe()
477 	pci->num_viewport = data->num_viewport;  in intel_pcie_probe()
488 	{ .compatible = "intel,lgm-pcie", .data = &pcie_data },
496 		.name = "intel-gw-pcie",