Searched +full:led +full:- +full:controller (Results 1 – 17 of 17) sorted by relevance
5 * Written by Hans at OK-Labs12 * KZM-ARM11-01 evaluation board, with a Freescale18 #include "hw/arm/fsl-imx31.h"21 #include "qemu/error-report.h"22 #include "system/address-spaces.h"25 #include "hw/char/serial-mm.h"31 * 0x00000000-0x7fffffff See i.MX31 SOC for support32 * 0x80000000-0x8fffffff RAM EMULATED33 * 0x90000000-0x9fffffff RAM EMULATED34 * 0xa0000000-0xafffffff Flash IGNORED[all …]
4 * Copyright (c) 2005-2007 CodeSourcery.19 #include "system/address-spaces.h"23 #include "qemu/error-report.h"30 #include "target/arm/cpu-qom.h"98 return s->cm_osc; in integratorcm_read()100 return s->cm_ctrl; in integratorcm_read()104 if (s->cm_lock == 0xa05f) { in integratorcm_read()107 return s->cm_lock; in integratorcm_read()113 return s->cm_auxosc; in integratorcm_read()115 return s->cm_sdram; in integratorcm_read()[all …]
9 * the COPYING file in the top-level directory.24 #include "hw/misc/led.h"25 #include "hw/qdev-properties.h"26 #include "system/block-backend.h"29 #include "qemu/error-report.h"32 #include "hw/qdev-clock.h"36 .board_id = -1, /* device-tree-only board */53 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */166 /* Quanta-Q71l hardware value */204 /* Qualcomm DC-SCM hardware value */[all …]
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>22 #include "qemu/error-report.h"23 #include "qemu/main-loop.h"26 #include "system/address-spaces.h"29 #include "hw/qdev-properties.h"44 #include "target/arm/cpu-qom.h"49 qemu_log_mask(LOG_GUEST_ERROR, "%s: %d-bit register %#08" HWADDR_PRIx "\n", in omap_log_badwidth()127 uint64_t distance = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->time; in omap_timer_read()129 if (timer->st && timer->enable && timer->rate) in omap_timer_read()130 return timer->val - muldiv64(distance >> (timer->ptv + 1), in omap_timer_read()[all …]
12 /* This is a model of the SCC (Serial Communication Controller)29 #include "hw/misc/mps2-scc.h"30 #include "hw/misc/led.h"31 #include "hw/qdev-properties.h"60 return extract32(s->id, 4, 8); in scc_partno()116 if (function != 1 || device >= s->num_oscclk) { in scc_cfg_write()123 s->oscclk[device] = value; in scc_cfg_write()134 if (function != 1 || device >= s->num_oscclk) { in scc_cfg_read()141 *value = s->oscclk[device]; in scc_cfg_read()154 r = s->cfg0; in mps2_scc_read()[all …]
4 * Copyright (c) 2006-2007 CodeSourcery.12 #include "hw/qdev-properties.h"93 return (s->sys_id >> 16) & 0xfff; in board_id()101 s->leds = 0; in arm_sysctl_reset()102 s->lockval = 0; in arm_sysctl_reset()103 s->cfgdata1 = 0; in arm_sysctl_reset()104 s->cfgdata2 = 0; in arm_sysctl_reset()105 s->flags = 0; in arm_sysctl_reset()106 s->resetlevel = 0; in arm_sysctl_reset()108 s->mb_clock[0] = 50000000; /* Static memory clock: 50MHz */ in arm_sysctl_reset()[all …]
13 * This is a model of the Serial Communication Controller (SCC)18 * + QOM property "scc-cfg4": value of the read-only CFG4 register19 * + QOM property "scc-aid": value of the read-only SCC_AID register20 * + QOM property "scc-id": value of the read-only SCC_ID register21 * + QOM property "scc-cfg0": reset value of the CFG0 register34 #include "hw/misc/led.h"37 #define TYPE_MPS2_SCC "mps2-scc"46 LEDState *led[8]; member
1 B-L475E-IOT01A IoT Node (``b-l475e-iot01a``)4 The B-L475E-IOT01A IoT Node uses the STM32L475VG SoC which is based on5 ARM Cortex-M4F core. It is part of STMicroelectronics7 ultra-low power series. The STM32L4x5 chip runs at up to 80 MHz and8 integrates 128 KiB of SRAM and up to 1MiB of Flash. The B-L475E-IOT01A board15 Currently B-L475E-IOT01A machines support the following devices:17 - Cortex-M4F based STM32L4x5 SoC18 - STM32L4x5 EXTI (Extended interrupts and events controller)19 - STM32L4x5 SYSCFG (System configuration controller)20 - STM32L4x5 RCC (Reset and clock control)[all …]
5 * Copyright (c) 2024 Mark Cave-Ayland15 #include "exec/cpu-interrupt.h"19 #include "hw/m68k/next-cube.h"28 #include "hw/qdev-properties.h"30 #include "qemu/error-report.h"48 #define TYPE_NEXT_RTC "next-rtc"66 #define TYPE_NEXT_SCSI "next-scsi"69 /* NeXT SCSI Controller */82 #define TYPE_NEXT_PC "next-pc"85 /* NeXT Peripheral Controller */[all …]
3 #include "qemu/host-utils.h"5 #include "qemu/error-report.h"7 #include "migration/qemu-file-types.h"17 /* TODO: remove fully only on state DISABLED and LED off.22 #define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */112 #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)122 #define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)124 #define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)145 return "power-only"; in shpc_slot_state_to_str()157 uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot); in shpc_get_status()[all …]
4 * Copyright (c) 2007-2008 Hervé Poussineau31 #include "hw/char/serial-mm.h"43 #include "hw/display/bochs-vbe.h"50 #include "qemu/error-report.h"53 #include "accel/tcg/cpu-ops.h"145 prom[i] = nd->macaddr.a[i]; in mips_jazz_init_net()151 prom[7] = 0xff - checksum; in mips_jazz_init_net()201 if (machine->ram_size > 256 * MiB) { in mips_jazz_init()206 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); in mips_jazz_init()211 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, in mips_jazz_init()[all …]
2 * SD Association Host Standard Specification v2.0 controller emulation10 * Based on MMC controller for Samsung S5PC1xx-based board emulation29 #include "qemu/error-report.h"32 #include "hw/qdev-properties.h"38 #include "sdhci-internal.h"43 #define TYPE_SDHCI_BUS "sdhci-bus"52 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); in DECLARE_INSTANCE_CHECKER()59 if (s->sd_spec_version >= 3) { in sdhci_check_capab_freq_range()68 "in range 0-63 only", desc); in sdhci_check_capab_freq_range()76 uint64_t msk = s->capareg; in sdhci_check_capareg()[all …]
26 * The controller is used in Sun4m systems in a slightly different33 #include "qemu/error-report.h"38 #include "hw/qdev-properties.h"39 #include "hw/qdev-properties-system.h"42 #include "system/block-backend.h"46 #include "qemu/main-loop.h"50 #include "fdc-internal.h"74 #define TYPE_FLOPPY_BUS "floppy-bus"88 bus->fdc = fdc; in floppy_bus_create()143 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },[all …]
... i-cache-sets d-cache-block-size i-cache-block-size tlb- ...
1 # -*- Mode: Python -*-5 # See the COPYING file in the top-level directory.12 { 'include': 'machine-common.json' }18 # targets. Run "./configure --help" in the project root directory,19 # and look for the \*-softmmu targets near the "--target-list" option.30 # "qemu-system-" prefix to produce the corresponding QEMU31 # executable name. This is true even for "qemu-system-x86_64".52 'data': [ 'uninitialized', 'stopped', 'check-stop', 'operating', 'load' ] }59 # @cpu-state: the virtual CPU's state68 'data': { 'cpu-state': 'S390CpuState',[all …]
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */124 /* 0x35-0x3b are reserved */130 /* Header type 1 (PCI-to-PCI bridges) */158 /* 0x35-0x3b is reserved */[all …]
10 consult qemu-devel and not any specific individual privately.23 W: Web-page with status/info59 ------------------------------63 L: qemu-devel@nongnu.org72 R: Philippe Mathieu-Daudé <philmd@linaro.org>75 F: docs/devel/build-environment.rst76 F: docs/devel/code-of-conduct.rst78 F: docs/devel/conflict-resolution.rst80 F: docs/devel/submitting-a-patch.rst81 F: docs/devel/submitting-a-pull-request.rst[all …]