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/qemu/target/hexagon/
H A Dop_helper.c1158 for (int lane = 0; lane < 8; lane++) { in HELPER() local
1160 unsigned char value = input->ub[(sizeof(MMVector) / 8) * lane + i]; in HELPER()
1164 env->VRegs[regno].uh[(sizeof(MMVector) / 16) * lane + element]++; in HELPER()
1173 for (int lane = 0; lane < 8; lane++) { in HELPER() local
1175 unsigned char value = input->ub[(sizeof(MMVector) / 8) * lane + i]; in HELPER()
1179 if (fGETQBIT(env->qtmp, sizeof(MMVector) / 8 * lane + i)) { in HELPER()
1181 (sizeof(MMVector) / 16) * lane + element]++; in HELPER()
/qemu/target/ppc/
H A Dtcg-excp_helper.c100 static uint32_t helper_SIMON_LIKE_32_64(uint32_t x, uint64_t key, uint32_t lane) in helper_SIMON_LIKE_32_64() argument
121 eff_k[4 * i + 0] = k[4 * i + ((0 + lane) % 4)]; in helper_SIMON_LIKE_32_64()
122 eff_k[4 * i + 1] = k[4 * i + ((1 + lane) % 4)]; in helper_SIMON_LIKE_32_64()
123 eff_k[4 * i + 2] = k[4 * i + ((2 + lane) % 4)]; in helper_SIMON_LIKE_32_64()
124 eff_k[4 * i + 3] = k[4 * i + ((3 + lane) % 4)]; in helper_SIMON_LIKE_32_64()
/qemu/target/arm/tcg/
H A Dneon-ls.decode43 # Neon load/store single structure to one lane
H A Dtranslate-mve.c962 * of the 32-bit elements in each lane of the input vectors, where the
2184 * corresponding to the lane of the vector register being accessed in DO_VABAV()
2227 * corresponding to the lane of the vector register being accessed in trans_VMOV_from_2gp()
H A Dtranslate-vfp.c580 * In a CPU with MVE, the VMOV (vector lane to general-purpose register) in mve_skip_vmov()
581 * and VMOV (general-purpose register to vector lane) insns are not in mve_skip_vmov()
587 * the beat corresponding to the lane of the vector register being in mve_skip_vmov()
H A Dtranslate-neon.c663 /* Neon load/store single structure to one lane */ in trans_VLDST_single()
1187 * duplicated into each lane of the immediate value. in do_2shift_narrow_32()
H A Dmve_helper.c64 * (1) by default, we update every lane in the vector in mve_element_mask()
71 * as VPR.P0: 0 to mask the lane, 1 if it is active. in mve_element_mask()
/qemu/target/hexagon/imported/mmvec/
H A Dext.idef381 * Unpack elements with zero/sign extend and cross lane permute
394 * Pack elements and cross lane permute
446 * Zero/Sign Extend with in-lane permute
1874 "Shuffle half words with in a lane",
1879 "Shuffle half words with in a lane",
1884 "Shuffle half words with in a lane",
1889 "Shuffle half words with in a lane",
2152 fHIDE(int lane;) \
2154 fVFOREACH(128, lane) { \
2156 unsigned char value = INPUTVEC.ub[(128/8)*lane+i]; \
[all …]
/qemu/include/standard-headers/linux/
H A Dpci_regs.h1149 #define PCI_SECPCI_LE_CTRL 0x0c /* Lane Equalization Control Register */
1152 #define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
1158 #define PCI_PL_32GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
1161 #define PCI_PL_64GT_LE_CTRL 0x20 /* Lane Equalization Control Register */
/qemu/hw/pci-host/
H A Ddesignware.c150 * PCIE lane (which in our case is irrelevant) and doesn't in designware_pcie_root_config_read()
/qemu/tcg/
H A Dtcg-op-gvec.c1926 should be the sign bit of each lane. This 6-operation form is more
/qemu/tcg/i386/
H A Dtcg-target.c.inc988 /* imm8 operand: all output lanes selected from input lane 0. */