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/qemu/hw/pci-bridge/
H A Dgen_pcie_root_port.c10 * See the COPYING file in the top-level directory.
18 #include "hw/qdev-properties.h"
19 #include "hw/qdev-properties-system.h"
23 #define TYPE_GEN_PCIE_ROOT_PORT "pcie-root-port"
56 assert(rc == -ENOTSUP); in gen_rp_interrupts_init()
73 return rp->migrate_msix; in gen_rp_test_migrate_msix()
84 rpc->parent_realize(dev, &local_err); in gen_rp_realize()
91 * reserving IO space led to worse issues in 6.1, when this hunk was in gen_rp_realize()
95 if (s->hide_native_hotplug_cap && grp->res_reserve.io == -1 && s->hotplug) { in gen_rp_realize()
96 grp->res_reserve.io = GEN_PCIE_ROOT_DEFAULT_IO_RANGE; in gen_rp_realize()
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H A Dcxl_root_port.c26 #include "hw/qdev-properties.h"
27 #include "hw/qdev-properties-system.h"
53 #define TYPE_CXL_ROOT_PORT "cxl-rp"
88 assert(rc == -ENOTSUP); in cxl_rp_interrupts_init()
101 uint32_t *reg_state = crp->cxl_cstate.crb.cache_mem_registers; in latch_registers()
102 uint32_t *write_msk = crp->cxl_cstate.crb.cache_mem_regs_write_mask; in latch_registers()
127 .cap = 0x26, /* IO, Mem, non-MLD */ in build_dvsecs()
152 CXLComponentState *cxl_cstate = &crp->cxl_cstate; in cxl_rp_realize()
153 ComponentRegisters *cregs = &cxl_cstate->crb; in cxl_rp_realize()
154 MemoryRegion *component_bar = &cregs->component_registers; in cxl_rp_realize()
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H A Dcxl_downstream.c8 * SPDX-License-Identifier: GPL-2.0-or-later
16 #include "hw/qdev-properties.h"
17 #include "hw/qdev-properties-system.h"
38 uint32_t *reg_state = dsp->cxl_cstate.crb.cache_mem_registers; in latch_registers()
39 uint32_t *write_msk = dsp->cxl_cstate.crb.cache_mem_regs_write_mask; in latch_registers()
50 CXLComponentState *cxl_cstate = &dsp->cxl_cstate; in cxl_dsp_dvsec_write_config()
52 if (range_contains(&cxl_cstate->dvsecs[EXTENSIONS_PORT_DVSEC], addr)) { in cxl_dsp_dvsec_write_config()
53 uint8_t *reg = &dev->config[addr]; in cxl_dsp_dvsec_write_config()
54 addr -= cxl_cstate->dvsecs[EXTENSIONS_PORT_DVSEC].lob; in cxl_dsp_dvsec_write_config()
108 .cap = 0x27, /* Cache, IO, Mem, non-MLD */ in build_dvsecs()
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H A Dcxl_upstream.c8 * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "hw/qdev-properties.h"
14 #include "hw/qdev-properties-system.h"
18 #include "hw/pci-bridge/cxl_upstream_port.h"
37 return &usp->cxl_cstate; in cxl_usp_to_cstate()
45 if (range_contains(&usp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC], addr)) { in cxl_usp_dvsec_write_config()
46 uint8_t *reg = &dev->config[addr]; in cxl_usp_dvsec_write_config()
47 addr -= usp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC].lob; in cxl_usp_dvsec_write_config()
67 pcie_doe_write_config(&usp->doe_cdat, address, val, len); in cxl_usp_write_config()
80 if (pcie_doe_read_config(&usp->doe_cdat, address, len, &val)) { in cxl_usp_read_config()
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/qemu/hw/char/
H A Ddebugcon.c2 * QEMU Bochs-style debug console ("port E9") emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
30 #include "chardev/char-fe.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-properties-system.h"
36 #define TYPE_ISA_DEBUGCON_DEVICE "isa-debugcon"
42 MemoryRegion io; member
55 unsigned width) in debugcon_ioport_write() argument
66 qemu_chr_fe_write_all(&s->chr, &ch, 1); in debugcon_ioport_write()
70 static uint64_t debugcon_ioport_read(void *opaque, hwaddr addr, unsigned width) in debugcon_ioport_read() argument
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/qemu/hw/acpi/
H A Dich9.c23 * Contributions after 2012-01-13 are licensed under the terms of the
41 #include "hw/mem/pc-dimm.h"
47 acpi_update_sci(&pm->acpi_regs, pm->irq); in ich9_pm_update_sci_fn()
50 static uint64_t ich9_gpe_readb(void *opaque, hwaddr addr, unsigned width) in ich9_gpe_readb() argument
53 return acpi_gpe_ioport_readb(&pm->acpi_regs, addr); in ich9_gpe_readb()
57 unsigned width) in ich9_gpe_writeb() argument
60 acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val); in ich9_gpe_writeb()
61 acpi_update_sci(&pm->acpi_regs, pm->irq); in ich9_gpe_writeb()
74 static uint64_t ich9_smi_readl(void *opaque, hwaddr addr, unsigned width) in ich9_smi_readl() argument
79 return pm->smi_en; in ich9_smi_readl()
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H A Dcore.c18 * Contributions after 2012-01-13 are licensed under the terms of the
26 #include "qemu/config-file.h"
28 #include "qapi/opts-visitor.h"
29 #include "qapi/qapi-events-run-state.h"
30 #include "qapi/qapi-visit-acpi.h"
31 #include "qemu/error-report.h"
58 static const char unsigned dfl_hdr[ACPI_TABLE_HDR_SIZE - ACPI_TABLE_PFX_SIZE] =
93 return (-sum) & 0xff; in acpi_checksum()
106 * @hdrs->file and @hdrs->data are ignored.
110 * The number of tables that can be installed is not limited, but the 16-bit
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H A Dich9_tco.c7 * See the COPYING file in the top-level directory.
35 int ticks = tr->tco.tmr & TCO_TMR_MASK; in tco_timer_reload()
39 tr->expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + nsec; in tco_timer_reload()
40 timer_mod(tr->tco_timer, tr->expire_time); in tco_timer_reload()
45 tr->expire_time = -1; in tco_timer_stop()
46 timer_del(tr->tco_timer); in tco_timer_stop()
54 uint32_t gcs = pci_get_long(lpc->chip_config + ICH9_CC_GCS); in tco_timer_expired()
56 trace_tco_timer_expired(tr->timeouts_no, in tco_timer_expired()
57 lpc->pin_strap.spkr_hi, in tco_timer_expired()
59 tr->tco.rld = 0; in tco_timer_expired()
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H A Dpiix4.c18 * Contributions after 2012-01-13 are licensed under the terms of the
27 #include "hw/qdev-properties.h"
39 #include "hw/mem/pc-dimm.h"
66 acpi_update_sci(&s->ar, s->irq); in pm_tmr_timer()
75 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE); in apm_ctrl_changed()
80 if (d->config[0x5b] & (1 << 1)) { in apm_ctrl_changed()
81 if (s->smi_irq) { in apm_ctrl_changed()
82 qemu_irq_raise(s->smi_irq); in apm_ctrl_changed()
91 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40)); in pm_io_space_update()
92 s->io_base &= 0xffc0; in pm_io_space_update()
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/qemu/hw/display/
H A Dqxl-render.c29 DisplaySurface *surface = qemu_console_surface(qxl->vga.con); in qxl_blit()
37 trace_qxl_render_blit(qxl->guest_primary.qxl_stride, in qxl_blit()
38 rect->left, rect->right, rect->top, rect->bottom); in qxl_blit()
39 src = qxl->guest_primary.data; in qxl_blit()
40 if (qxl->guest_primary.qxl_stride < 0) { in qxl_blit()
43 src += (qxl->guest_primary.surface.height - rect->top - 1) * in qxl_blit()
44 qxl->guest_primary.abs_stride; in qxl_blit()
46 src += rect->top * qxl->guest_primary.abs_stride; in qxl_blit()
48 dst += rect->top * qxl->guest_primary.abs_stride; in qxl_blit()
49 src += rect->left * qxl->guest_primary.bytes_pp; in qxl_blit()
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H A Dxenfb.c4 * Copyright IBM, Corp. 2005-2006
5 * Copyright Red Hat, Inc. 2006-2008
33 #include "hw/xen/xen-legacy-backend.h"
35 #include "hw/xen/interface/io/fbif.h"
36 #include "hw/xen/interface/io/kbdif.h"
37 #include "hw/xen/interface/io/protocols.h"
45 /* -------------------------------------------------------------------- */
70 int width; member
87 /* -------------------------------------------------------------------- */
94 if (xenstore_read_fe_uint64(&c->xendev, "page-ref", &val) == -1) in common_bind()
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H A Dvmware_vga.c2 * QEMU VMware-SVGA "chipset".
33 #include "hw/qdev-properties.h"
45 /* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */
87 #define TYPE_VMWARE_SVGA "vmware-svga"
192 * FIFO offsets (seen as an array of 32-bit words)
319 trace_vmware_verify_rect_surface_bound_exceeded(name, "width", in vmsvga_verify_rect()
356 DisplaySurface *surface = qemu_console_surface(s->vga.con); in vmsvga_update_rect()
359 int width; in vmsvga_update_rect() local
373 width = surface_bytes_per_pixel(surface) * w; in vmsvga_update_rect()
375 src = s->vga.vram_ptr + start; in vmsvga_update_rect()
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H A Dg364fb.c4 * Copyright (c) 2007-2011 Herve Poussineau
24 #include "hw/qdev-properties.h"
26 #include "qemu/error-report.h"
48 uint32_t width, height; /* in pixels */ member
73 return memory_region_snapshot_get_dirty(&s->mem_vram, snap, page, G364_PAGE_SIZE); in check_dirty()
78 DisplaySurface *surface = qemu_console_surface(s->con); in g364fb_draw_graphic8()
116 xmin = s->width; in g364fb_draw_graphic8()
118 ymin = s->height; in g364fb_draw_graphic8()
121 if (!(s->ctla & CTLA_NO_CURSOR)) { in g364fb_draw_graphic8()
122 xcursor = s->cursor_position >> 12; in g364fb_draw_graphic8()
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/qemu/hw/misc/
H A Ddebugexit.c12 #include "hw/qdev-properties.h"
17 #define TYPE_ISA_DEBUG_EXIT_DEVICE "isa-debug-exit"
25 MemoryRegion io; member
34 unsigned width) in debug_exit_write() argument
53 memory_region_init_io(&isa->io, OBJECT(dev), &debug_exit_ops, isa, in debug_exit_realizefn()
54 TYPE_ISA_DEBUG_EXIT_DEVICE, isa->iosize); in debug_exit_realizefn()
56 isa->iobase, &isa->io); in debug_exit_realizefn()
68 dc->realize = debug_exit_realizefn; in debug_exit_class_initfn()
70 set_bit(DEVICE_CATEGORY_MISC, dc->categories); in debug_exit_class_initfn()
/qemu/ui/
H A Dspice-display.c19 #include "ui/qemu-spice.h"
20 #include "qemu/error-report.h"
23 #include "qemu/main-loop.h"
29 #include "ui/spice-display.h"
31 #include "standard-headers/drm/drm_fourcc.h"
37 return r->top == r->bottom || r->left == r->right; in qemu_spice_rect_is_empty()
51 dest->top = MIN(dest->top, r->top); in qemu_spice_rect_union()
52 dest->left = MIN(dest->left, r->left); in qemu_spice_rect_union()
53 dest->bottom = MAX(dest->bottom, r->bottom); in qemu_spice_rect_union()
54 dest->right = MAX(dest->right, r->right); in qemu_spice_rect_union()
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H A Dui-qmp-cmds.c10 * the COPYING file in the top-level directory.
12 * Contributions after 2012-01-13 are licensed under the terms of the
18 #include "io/channel-file.h"
19 #include "monitor/qmp-helpers.h"
20 #include "qapi/qapi-commands-ui.h"
26 #include "ui/dbus-display.h"
27 #include "ui/qemu-spice.h"
36 if (opts->protocol == DISPLAY_PROTOCOL_SPICE) { in qmp_set_password()
40 rc = qemu_spice.set_passwd(opts->password, in qmp_set_password()
41 opts->connected == SET_PASSWORD_ACTION_FAIL, in qmp_set_password()
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H A Dinput-barrier.c2 * SPDX-License-Identifier: GPL-2.0-or-later
5 * See the COPYING file in the top-level directory.
9 * - Enable SSL
10 * - Manage SetOptions/ResetOptions commands
15 #include "qemu/main-loop.h"
19 #include "io/channel-socket.h"
25 #include "input-barrier.h"
27 #define TYPE_INPUT_BARRIER "input-barrier"
43 int16_t width, height; member
131 l -= size; \
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/qemu/docs/specs/
H A Dpci-testdev.rst5 ``pci-testdev`` is a device used for testing low level IO.
8 Each of BAR 0+1 can be memory or IO. Guests must detect
14 .. code-block:: c
17 uint8_t test; /* write-only, starts a given test number */
19 * read-only, type and width of access for a given test.
24 uint32_t offset; /* read-only, offset in this BAR for a given test */
25 uint32_t data; /* read-only, data to use for a given test */
27 uint8_t name[]; /* for debugging. 0-terminated ASCII string. */
/qemu/include/hw/xen/interface/arch-x86/
H A Dcpuid.h1 /* SPDX-License-Identifier: MIT */
3 * arch-x86/cpuid.h
30 * EAX: Largest Xen-information leaf. All leaves up to an including @EAX
32 * EBX-EDX: "XenVMMXenVMM" signature, allowing positive identification
43 * EBX-EDX: Reserved (currently all zeroes).
50 * EBX: Base address of Xen-specific MSRs.
61 * Sub-leaf 0: EAX: bit 0: emulated tsc
68 * Sub-leaf 1: EAX: tsc offset low part
70 * ECX: multiplicator for tsc->ns conversion
71 * EDX: shift amount for tsc->ns conversion
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/qemu/pc-bios/dtb/
H A Dpetalogix-ml605.dts5 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
11 #address-cells = < 0x01 >;
12 #size-cells = < 0x01 >;
22 ethernet0 = "/axi/axi-ethernet@82780000";
28 stdout-path = "/axi/serial@83e00000";
32 #address-cells = < 0x01 >;
34 #size-cells = < 0x00 >;
37 clock-frequency = < 0xbebc200 >;
38 compatible = "xlnx,microblaze-8.10.a";
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/qemu/scripts/
H A Ddecodetree.py23 import io
50 re_C_ident = '[a-zA-Z][a-zA-Z0-9_]*'
53 re_arg_ident = '&[a-zA-Z0-9_]*'
54 re_fld_ident = '%[a-zA-Z0-9_]*'
55 re_fmt_ident = '@[a-zA-Z0-9_]*'
56 re_pat_ident = '[a-zA-Z0-9_]*'
70 # (That is, if graph contains "A" -> ["B", "C"] then we must output
85 # https://code.activestate.com/recipes/578272-topological-sort/
112 - set(data.keys()))
120 data = {item: (dep - ordered)
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/qemu/docs/
H A Digd-assign.txt1 Intel Graphics Device (IGD) assignment with vfio-pci
4 Using vfio-pci, we can passthrough Intel Graphics Device (IGD) to guest, either
16 (*-Required by)
19 |---------------------------------------------|-------|---------|-------|---------|
30 For #1, the "x-igd-opregion=on" option exposes a copy of host IGD OpRegion to
33 For #2, "x-igd-lpc=on" option copies the IDs of host LPC bridge and host bridge
42 For #5, "x-vga=on" enables guest access to standard VGA IO/MMIO ranges.
57 x-igd-opregion=on,x-igd-lpc=on,x-vga=on
60 "x-igd-legacy-mode=on" to force enabling legacy mode, this also checks if the
62 fail immediately. Users can also set "x-igd-legacy-mode=off" to disable legacy
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/qemu/hw/riscv/
H A Driscv-iommu.h2 * QEMU emulation of an RISC-V IOMMU
4 * Copyright (C) 2022-2023 Rivos Inc.
23 #include "hw/qdev-properties.h"
26 #include "hw/riscv/riscv-iommu-bits.h"
36 uint32_t pid_bits; /* process identifier width */
37 uint32_t bus; /* PCI bus mapping for non-root endpoints */
43 bool enable_off; /* Enable out-of-reset OFF mode (DMA disabled) */
46 bool enable_s_stage; /* Enable S/VS-Stage translation */
47 bool enable_g_stage; /* Enable G-Stage translation */
73 GHashTable *iot_cache; /* IO Translated Address Cache */
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/qemu/docs/devel/
H A Dmulti-thread-tcg.rst2 Copyright (c) 2015-2020 Linaro Ltd.
5 later. See the COPYING file in the top-level directory.
10 Multi-threaded TCG
13 This document outlines the design for multi-threaded TCG (a.k.a MTTCG)
14 system-mode emulation. user-mode emulation has always mirrored the
17 linux-user emulation.
19 The original system-mode TCG implementation was single threaded and
20 dealt with multiple CPUs with simple round-robin scheduling. This
22 being emulated gained additional cores and per-core performance gains
29 user-space thread. This is enabled by default for all FE/BE
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/qemu/hw/xtensa/
H A Dxtfpga.c35 #include "hw/qdev-properties.h"
39 #include "hw/char/serial-mm.h"
47 #include "qemu/error-report.h"
64 const hwaddr *io; member
78 s->leds = 0; in xtfpga_fpga_reset()
79 s->switches = 0; in xtfpga_fpga_reset()
92 return s->freq; in xtfpga_fpga_read()
95 return s->leds; in xtfpga_fpga_read()
98 return s->switches; in xtfpga_fpga_read()
110 s->leds = val; in xtfpga_fpga_write()
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