| /linux-6.8/drivers/gpu/drm/xe/ |
| D | xe_gt_tlb_invalidation.c | 33 drm_err(>_to_xe(gt)->drm, "gt%d: TLB invalidation fence timeout, seqno=%d recv=%d", in xe_gt_tlb_fence_timeout()
49 * xe_gt_tlb_invalidation_init - Initialize GT TLB invalidation state
52 * Initialize GT TLB invalidation state, purely software initialization, should
86 * xe_gt_tlb_invalidation_reset - Initialize GT TLB invalidation reset
89 * Signal any pending invalidation fences, should be called during a GT reset
148 * XXX: The seqno algorithm relies on TLB invalidation being processed in send_tlb_invalidation()
203 * xe_gt_tlb_invalidation_guc - Issue a TLB invalidation on this GT for the GuC
206 * Issue a TLB invalidation for the GuC. Completion of TLB is asynchronous and
225 * xe_gt_tlb_invalidation_vma - Issue a TLB invalidation on this GT for a VMA
227 * @fence: invalidation fence which will be signal on TLB invalidation
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| D | xe_gt_tlb_invalidation_types.h | 12 * struct xe_gt_tlb_invalidation_fence - XE GT TLB invalidation fence
15 * invalidation completion.
22 /** @seqno: seqno of TLB invalidation to signal fence one */
24 /** @invalidation_time: time of TLB invalidation */
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| D | xe_gt_types.h | 153 /** @tlb_invalidation: TLB invalidation state */
155 /** @seqno: TLB invalidation seqno, protected by CT lock */
159 * @seqno_recv: last received TLB invalidation seqno, protected by CT lock
177 /** @fence_context: context for TLB invalidation fences */
180 * @fence_seqno: seqno to TLB invalidation fences, protected by
184 /** @lock: protects TLB invalidation fences */
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| D | xe_vm_doc.h | 182 * invalidation). The first operation waits on the VM's
207 * Invalidation
211 * whenever it wants. We register an invalidation MMU notifier to alert XE when
212 * a user poiter is about to move. The invalidation notifier needs to block
220 * rebind the userptr. The invalidation MMU notifier kicks the rebind worker
346 * invalidation responses are also in the critical path so these can also be
371 * Issue blocking TLB invalidation |
402 * Cavets with eviction / user pointer invalidation
405 * In the case of eviction and user pointer invalidation on a faulting VM, there
409 * neeeed. In both the case of eviction and user pointer invalidation locks are
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| /linux-6.8/arch/arm64/include/asm/ |
| D | tlbflush.h | 95 * the level at which the invalidation must take place. If the level is
96 * wrong, no invalidation may take place. In the case where the level
98 * a non-hinted invalidation. Any provided level outside the hint range
99 * will also cause fall-back to non-hinted invalidation.
101 * For Stage-2 invalidation, use the level values provided to that effect
172 * TLB Invalidation
175 * This header file implements the low-level TLB invalidation routines
178 * Every invalidation operation uses the following template:
182 * DSB ISH // Ensure the TLB invalidation has completed
187 * The following functions form part of the "core" TLB invalidation API,
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| D | kvm_pgtable.h | 246 * TLB invalidation.
398 * to freeing and therefore no TLB invalidation is performed.
434 * TLB invalidation is performed for each page-table entry cleared during the
493 * to freeing and therefore no TLB invalidation is performed.
504 * freeing and therefore no TLB invalidation is performed.
521 * invalidation or CMOs are performed.
596 * TLB invalidation is performed for each page-table entry cleared during the
608 * without TLB invalidation.
672 * TLB invalidation is performed after updating the entry. Software bits cannot
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| /linux-6.8/drivers/gpu/drm/xe/abi/ |
| D | guc_actions_abi.h | 187 /* Flush PPC or SMRO caches along with TLB invalidation request */
198 * 0: Heavy mode of Invalidation:
199 * The pipeline of the engine(s) for which the invalidation is targeted to is
201 * Observed before completing the TLB invalidation
202 * 1: Lite mode of Invalidation:
205 * completing TLB invalidation.
206 * Light Invalidation Mode is to be used only when
208 * for the in-flight transactions across the TLB invalidation. In other words,
209 * this mode can be used when the TLB invalidation is intended to clear out the
210 * stale cached translations that are no longer in use. Light Invalidation Mode
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| /linux-6.8/drivers/gpu/drm/i915/gt/ |
| D | intel_tlb.c | 18 * HW architecture suggest typical invalidation time at 40us,
26 * On Xe_HP the TLB invalidation registers are located at the same MMIO offsets
100 "%s TLB invalidation did not complete in %ums!\n", in mmio_invalidate_full()
143 * Only perform GuC TLB invalidation if GuC is ready. in intel_gt_invalidate_tlb_full()
146 * any TLB invalidation path here unnecessary. in intel_gt_invalidate_tlb_full()
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| /linux-6.8/include/uapi/linux/ |
| D | iommufd.h | 618 * enum iommu_hwpt_invalidate_data_type - IOMMU HWPT Cache Invalidation
620 * @IOMMU_HWPT_INVALIDATE_DATA_VTD_S1: Invalidation data for VTD_S1
628 * stage-1 cache invalidation
629 * @IOMMU_VTD_INV_FLAGS_LEAF: Indicates whether the invalidation applies
638 * struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
646 * The Intel VT-d specific invalidation data for user-managed stage-1 cache
647 * invalidation in nested translation. Userspace uses this structure to
665 * @hwpt_id: ID of a nested HWPT for cache invalidation
666 * @data_uptr: User pointer to an array of driver-specific cache invalidation
669 * type of all the entries in the invalidation request array. It
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| /linux-6.8/arch/arm64/kvm/hyp/nvhe/ |
| D | tlb.c | 26 * being either ish or nsh, depending on the invalidation in __tlb_switch_to_guest()
98 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa()
101 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa()
128 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa_nsh()
131 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa_nsh()
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| /linux-6.8/drivers/gpu/drm/i915/gt/uc/abi/ |
| D | guc_actions_abi.h | 196 * 0: Heavy mode of Invalidation:
197 * The pipeline of the engine(s) for which the invalidation is targeted to is
199 * Observed before completing the TLB invalidation
200 * 1: Lite mode of Invalidation:
203 * completing TLB invalidation.
204 * Light Invalidation Mode is to be used only when
206 * for the in-flight transactions across the TLB invalidation. In other words,
207 * this mode can be used when the TLB invalidation is intended to clear out the
208 * stale cached translations that are no longer in use. Light Invalidation Mode
209 * is much faster than the Heavy Invalidation Mode, as it does not wait for the
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| /linux-6.8/drivers/iommu/intel/ |
| D | dmar.c | 1217 return "Context-cache Invalidation"; in qi_type_string()
1219 return "IOTLB Invalidation"; in qi_type_string()
1221 return "Device-TLB Invalidation"; in qi_type_string()
1223 return "Interrupt Entry Cache Invalidation"; in qi_type_string()
1225 return "Invalidation Wait"; in qi_type_string()
1227 return "PASID-based IOTLB Invalidation"; in qi_type_string()
1229 return "PASID-cache Invalidation"; in qi_type_string()
1231 return "PASID-based Device-TLB Invalidation"; in qi_type_string()
1246 pr_err("VT-d detected Invalidation Queue Error: Reason %llx", in qi_dump_fault()
1249 pr_err("VT-d detected Invalidation Time-out Error: SID %llx", in qi_dump_fault()
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| D | pasid.c | 476 * - PASID-selective-within-Domain PASID-cache invalidation in intel_pasid_setup_dirty_tracking()
478 * - Domain-selective IOTLB invalidation in intel_pasid_setup_dirty_tracking()
480 * - PASID-selective PASID-based IOTLB invalidation in intel_pasid_setup_dirty_tracking()
482 * - Global Device-TLB invalidation to affected functions in intel_pasid_setup_dirty_tracking()
484 * - PASID-based Device-TLB invalidation (with S=1 and in intel_pasid_setup_dirty_tracking()
557 * VT-d spec 3.4 table23 states guides for cache invalidation: in intel_pasid_setup_page_snoop_control()
559 * - PASID-selective-within-Domain PASID-cache invalidation in intel_pasid_setup_page_snoop_control()
560 * - PASID-selective PASID-based IOTLB invalidation in intel_pasid_setup_page_snoop_control()
562 * - Global Device-TLB invalidation to affected functions in intel_pasid_setup_page_snoop_control()
564 * - PASID-based Device-TLB invalidation (with S=1 and in intel_pasid_setup_page_snoop_control()
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| /linux-6.8/drivers/infiniband/ulp/rtrs/ |
| D | README | 54 The procedure is the default behaviour of the driver. This invalidation and
165 the user header, flags (specifying if memory invalidation is necessary) and the
169 attaches an invalidation message if requested and finally an "empty" rdma
176 or in case client requested invalidation:
184 the user header, flags (specifying if memory invalidation is necessary) and the
190 attaches an invalidation message if requested and finally an "empty" rdma
201 or in case client requested invalidation:
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| /linux-6.8/arch/powerpc/include/asm/ |
| D | pnv-ocxl.h | 19 /* Radix Invalidation Control
28 /* Invalidation Criteria
35 /* Invalidation Flag */
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| /linux-6.8/arch/arm64/kvm/hyp/vhe/ |
| D | tlb.c | 111 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa()
114 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa()
143 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa_nsh()
146 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa_nsh()
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| /linux-6.8/arch/arm/mach-versatile/ |
| D | dcscb_setup.S | 20 * A15/A7 may not require explicit L2 invalidation on reset, dependent
23 * or invalidation is not required.
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| /linux-6.8/Documentation/filesystems/caching/ |
| D | netfs-api.rst | 36 (8) Data file invalidation
39 (11) Page release and invalidation
285 The read operation will fail with ESTALE if invalidation occurred whilst the
302 Data File Invalidation
319 This increases the invalidation counter in the cookie to cause outstanding
324 Invalidation runs asynchronously in a worker thread so that it doesn't block
427 Page Release and Invalidation
442 Page release and page invalidation should also wait for any mark left on the
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| /linux-6.8/Documentation/gpu/ |
| D | drm-vm-bind-locking.rst | 87 notifier invalidation. This is not a real seqlock but described in
95 invalidation notifiers.
103 invalidation. The userptr notifier lock is per gpu_vm.
406 <Invalidation example>` below). Note that when the core mm decides to
435 // invalidation notifier running anymore.
449 // of the MMU invalidation notifier. Hence the
476 The userptr gpu_vma MMU invalidation notifier might be called from
495 // invalidation callbacks, the mmu notifier core will flip
504 When this invalidation notifier returns, the GPU can no longer be
564 invalidation notifier where zapping happens. Hence, if the
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| /linux-6.8/drivers/cxl/ |
| D | Kconfig | 136 to invalidate caches when those events occur. If that invalidation
138 invalidation failure are due to the CPU not providing a cache
139 invalidation mechanism. For example usage of wbinvd is restricted to
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| /linux-6.8/include/linux/ |
| D | memregion.h | 41 * contents while performing the invalidation. It is only exported for
59 WARN_ON_ONCE("CPU cache invalidation required"); in cpu_cache_invalidate_memregion()
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| /linux-6.8/drivers/misc/sgi-gru/ |
| D | grutlbpurge.c | 32 /* ---------------------------------- TLB Invalidation functions --------
88 * General purpose TLB invalidation function. This function scans every GRU in
117 * To help improve the efficiency of TLB invalidation, the GMS data
122 * provide the callbacks for TLB invalidation. The GMS contains:
139 * zero to force a full TLB invalidation. This is fast but will
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| /linux-6.8/drivers/gpu/drm/amd/amdgpu/ |
| D | gmc_v11_0.c | 227 * Directly use kiq to do the vm invalidation instead in gmc_v11_0_flush_gpu_tlb()
241 * off cycle, add semaphore acquire before invalidation and semaphore in gmc_v11_0_flush_gpu_tlb()
242 * release after invalidation to avoid entering power gated state in gmc_v11_0_flush_gpu_tlb()
276 /* Issue additional private vm invalidation to MMHUB */ in gmc_v11_0_flush_gpu_tlb()
283 /* Issue private invalidation */ in gmc_v11_0_flush_gpu_tlb()
285 /* Read back to ensure invalidation is done*/ in gmc_v11_0_flush_gpu_tlb()
302 * @inst: is used to select which instance of KIQ to use for the invalidation
343 * off cycle, add semaphore acquire before invalidation and semaphore in gmc_v11_0_emit_flush_gpu_tlb()
344 * release after invalidation to avoid entering power gated state in gmc_v11_0_emit_flush_gpu_tlb()
372 * add semaphore release after invalidation, in gmc_v11_0_emit_flush_gpu_tlb()
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| /linux-6.8/arch/powerpc/kernel/ |
| D | l2cr_6xx.S | 60 - L2I set to perform a global invalidation
111 /* Before we perform the global invalidation, we must disable dynamic
207 /* Perform a global invalidation */
223 /* Wait for the invalidation to complete */
342 /* Perform a global invalidation */
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| /linux-6.8/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| D | l2_cache.json | 12 …he L2 (from other CPUs) which return data even if the snoops cause an invalidation. L2 cache line …
44 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca…
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