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12

/linux-6.15/Documentation/devicetree/bindings/clock/
Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
14 model to control the clock gates for the peripherals. An LPCG module
24 include/dt-bindings/clock/imx8-lpcg.h
29 - const: fsl,imx8qxp-lpcg
[all …]
/linux-6.15/arch/arm64/boot/dts/freescale/
Dimx8-ss-mipi0.dtsi1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_mipi0>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 irqsteer_mipi0: interrupt-controller@56220000 {
15 compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
[all …]
Dimx8-ss-mipi1.dtsi1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_mipi1>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 irqsteer_mipi1: interrupt-controller@57220000 {
15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
[all …]
Dimx8-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/dma/fsl-edma.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
11 dma_ipg_clk: clock-dma-ipg {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <120000000>;
15 clock-output-names = "dma_ipg_clk";
[all …]
Dimx8-ss-audio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-clock.h>
8 #include <dt-bindings/clock/imx8-lpcg.h>
9 #include <dt-bindings/dma/fsl-edma.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
12 audio_ipg_clk: clock-audio-ipg {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <120000000>;
[all …]
Dimx8-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 conn_axi_clk: clock-conn-axi {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <333333333>;
14 clock-output-names = "conn_axi_clk";
17 conn_ahb_clk: clock-conn-ahb {
[all …]
Dimx8-ss-lsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 lsio_bus_clk: clock-lsio-bus {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <100000000>;
14 clock-output-names = "lsio_bus_clk";
18 compatible = "simple-bus";
[all …]
Dimx8-ss-lvds0.dtsi1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 #address-cells = <1>;
10 #size-cells = <1>;
13 qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 {
14 compatible = "fsl,imx8qxp-lpcg";
16 #clock-cells = <1>;
17 clock-output-names = "lvds0_lis_lpcg_ipg_clk";
18 power-domains = <&pd IMX_SC_R_MIPI_1>;
21 qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c {
[all …]
Dimx8qm-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 compatible = "fsl,imx8q-pcie";
19 reg-names = "dbi", "config";
22 #interrupt-cells = <1>;
24 interrupt-names = "msi";
25 #address-cells = <3>;
26 #size-cells = <2>;
[all …]
Dimx8-ss-lvds1.dtsi1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_lvds1>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 irqsteer_lvds1: interrupt-controller@57240000 {
15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
[all …]
Dimx8qm-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 /delete-node/ &adma_pwm;
8 /delete-node/ &adma_pwm_lpcg;
11 uart4_lpcg: clock-controller@5a4a0000 {
12 compatible = "fsl,imx8qxp-lpcg";
14 #clock-cells = <1>;
17 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
18 clock-output-names = "uart4_lpcg_baud_clk",
20 power-domains = <&pd IMX_SC_R_UART_4>;
[all …]
Dimx8-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/phy/phy.h>
9 hsio_axi_clk: clock-hsio-axi {
10 compatible = "fixed-clock";
11 #clock-cells = <0>;
12 clock-frequency = <400000000>;
13 clock-output-names = "hsio_axi_clk";
16 hsio_per_clk: clock-hsio-per {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
Dimx8-ss-cm40.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/firmware/imx/rsrc.h>
9 cm40_ipg_clk: clock-cm40-ipg {
10 compatible = "fixed-clock";
11 #clock-cells = <0>;
12 clock-frequency = <132000000>;
13 clock-output-names = "cm40_ipg_clk";
17 compatible = "simple-bus";
18 #address-cells = <1>;
19 #size-cells = <1>;
[all …]
Dimx8qm-ss-audio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 /delete-node/ &acm;
8 /delete-node/ &sai4;
9 /delete-node/ &sai5;
10 /delete-node/ &sai4_lpcg;
11 /delete-node/ &sai5_lpcg;
37 power-domains = <&pd IMX_SC_R_ASRC_0>;
43 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>;
44 clock-output-names = "asrc0_lpcg_ipg_clk", "asrc0_lpcg_mem_clk";
67 power-domains = <&pd IMX_SC_R_ASRC_1>;
[all …]
Dimx8dxl-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /delete-node/ &enet1_lpcg;
7 /delete-node/ &fec2;
10 conn_enet0_root_clk: clock-conn-enet0-root {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <250000000>;
14 clock-output-names = "conn_enet0_root_clk";
17 clk_dummy: clock-dummy {
18 compatible = "fixed-clock";
[all …]
Dimx8-ss-cm41.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <dt-bindings/clock/imx8-lpcg.h>
10 cm41_ipg_clk: clock-cm41-ipg {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <132000000>;
14 clock-output-names = "cm41_ipg_clk";
18 compatible = "simple-bus";
19 #address-cells = <1>;
[all …]
Dimx8-ss-img.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2021 NXP
6 img_ipg_clk: clock-img-ipg {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <200000000>;
10 clock-output-names = "img_ipg_clk";
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
[all …]
Dimx8qxp-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 phyx1_lpcg: clock-controller@5f090000 {
9 compatible = "fsl,imx8qxp-lpcg";
13 #clock-cells = <1>;
14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
16 clock-output-names = "hsio_phyx1_pclk",
20 power-domains = <&pd IMX_SC_R_SERDES_1>;
24 compatible = "fsl,imx8qxp-hsio";
29 reg-names = "reg", "phy", "ctrl", "misc";
35 clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr",
[all …]
Dimx8dxl-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 phyx1_lpcg: clock-controller@5f090000 {
8 compatible = "fsl,imx8qxp-lpcg";
12 #clock-cells = <1>;
13 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
15 clock-output-names = "hsio_phyx1_pclk",
19 power-domains = <&pd IMX_SC_R_SERDES_1>;
23 compatible = "fsl,imx8qxp-hsio";
28 reg-names = "reg", "phy", "ctrl", "misc";
34 clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr",
[all …]
/linux-6.15/drivers/clk/imx/
Dclk-imx8qxp-lpcg.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
16 #include "clk-scu.h"
17 #include "clk-imx8qxp-lpcg.h"
19 #include <dt-bindings/clock/imx8-clock.h>
22 * struct imx8qxp_lpcg_data - Description of one LPCG clock
27 * @offset: offset of this LPCG clock
28 * @bit_idx: bit index of this LPCG clock
31 * This structure describes one LPCG clock
44 * struct imx8qxp_ss_lpcg - Description of one subsystem LPCG clocks
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-composite-93.o
8 mxc-clk-objs += clk-fracn-gppll.o
9 mxc-clk-objs += clk-cpu.o
10 mxc-clk-objs += clk-divider-gate.o
11 mxc-clk-objs += clk-fixup-div.o
[all …]
/linux-6.15/Documentation/devicetree/bindings/bus/
Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
35 - $ref: simple-pm-bus.yaml#
37 # We need a select here so we don't match all nodes with 'simple-pm-bus'.
43 - fsl,imx8qxp-display-pixel-link-msi-bus
44 - fsl,imx8qm-display-pixel-link-msi-bus
[all …]
/linux-6.15/Documentation/devicetree/bindings/media/
Dnxp,imx8-jpeg.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mirela Rabulea <mirela.rabulea@nxp.com>
12 description: |-
13 The JPEG decoder/encoder present in iMX8QXP and iMX8QM SoCs is an
14 ISO/IEC 10918-1 JPEG standard compliant decoder/encoder, for Baseline
20 - items:
22 - nxp,imx8qxp-jpgdec
[all …]
/linux-6.15/Documentation/devicetree/bindings/mfd/
Dfsl,imx8qxp-csr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
17 use-case is for some other nodes to acquire a reference to the syscon node
18 by phandle, and the other typical use-case is that the operating system
23 pattern: "^syscon@[0-9a-f]+$"
27 - enum:
28 - fsl,imx8qxp-mipi-lvds-csr
[all …]
/linux-6.15/Documentation/devicetree/bindings/display/bridge/
Dfsl,imx8qxp-pixel-combiner.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
23 - fsl,imx8qm-pixel-combiner
24 - fsl,imx8qxp-pixel-combiner
26 "#address-cells":
29 "#size-cells":
38 clock-names:
[all …]

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