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Searched +full:imx8 +full:- +full:clock (Results 1 – 10 of 10) sorted by relevance

/linux-5.10/Documentation/devicetree/bindings/net/
Dimx-dwmac.txt1 IMX8 glue layer controller, NXP imx8 families support Synopsys MAC 5.10a IP.
9 - compatible: Should be "nxp,imx8mp-dwmac-eqos" to select glue layer
10 and "snps,dwmac-5.10a" to select IP version.
11 - clocks: Must contain a phandle for each entry in clock-names.
12 - clock-names: Should be "stmmaceth" for the host clock.
13 Should be "pclk" for the MAC apb clock.
14 Should be "ptp_ref" for the MAC timer clock.
15 Should be "tx" for the MAC RGMII TX clock:
16 Should be "mem" for EQOS MEM clock.
17 - "mem" clock is required for imx8dxl platform.
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/linux-5.10/Documentation/devicetree/bindings/clock/
Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
14 model to control the clock gates for the peripherals. An LPCG module
17 This level of clock gating is provided after the clocks are generated
18 by the SCU resources and clock controls. Thus even if the clock is
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/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8qxp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
14 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
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/linux-5.10/Documentation/devicetree/bindings/dsp/
Dfsl,dsp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Baluta <daniel.baluta@nxp.com>
14 advanced pre- and post- audio processing.
19 - fsl,imx8qxp-dsp
20 - fsl,imx8qm-dsp
21 - fsl,imx8mp-dsp
28 - description: ipg clock
29 - description: ocram clock
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/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-imx.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwmac-imx.c - DWMAC Specific Glue layer for NXP imx8
55 struct imx_priv_data *dwmac = plat_dat->bsp_priv; in imx8mp_set_intf_mode()
58 switch (plat_dat->interface) { in imx8mp_set_intf_mode()
64 val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL); in imx8mp_set_intf_mode()
75 plat_dat->interface); in imx8mp_set_intf_mode()
76 return -EINVAL; in imx8mp_set_intf_mode()
80 return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, in imx8mp_set_intf_mode()
99 plat_dat = dwmac->plat_dat; in imx_dwmac_init()
101 ret = clk_prepare_enable(dwmac->clk_mem); in imx_dwmac_init()
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/linux-5.10/drivers/clk/imx/
Dclk-imx8qxp-lpcg.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
16 #include "clk-scu.h"
17 #include "clk-imx8qxp-lpcg.h"
19 #include <dt-bindings/clock/imx8-clock.h>
22 * struct imx8qxp_lpcg_data - Description of one LPCG clock
23 * @id: clock ID
24 * @name: clock name
25 * @parent: parent clock name
26 * @flags: common clock flags
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Dclk-imx8qxp.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
15 #include "clk-scu.h"
17 #include <dt-bindings/clock/imx8-clock.h>
18 #include <dt-bindings/firmware/imx/rsrc.h>
22 struct device_node *ccm_node = pdev->dev.of_node; in imx8qxp_clk_probe()
31 clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws, in imx8qxp_clk_probe()
34 return -ENOMEM; in imx8qxp_clk_probe()
36 clk_data->num = IMX_SCU_CLK_END; in imx8qxp_clk_probe()
37 clks = clk_data->hws; in imx8qxp_clk_probe()
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/linux-5.10/sound/soc/fsl/
Dfsl_asrc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * fsl_asrc.h - Freescale ASRC ALSA SoC header file
122 #define ASRCNCR_ANCi_MASK(i, b) (((1 << b) - 1) << ASRCNCR_ANCi_SHIFT(i, b))
136 #define ASRCFG_POSTMODi_MASK(i) (((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i))
144 #define ASRCFG_PREMODi_MASK(i) (((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i))
154 #define ASRCSR_AxCSi_MASK ((1 << ASRCSR_AxCSi_WIDTH) - 1)
156 #define ASRCSR_AOCSi_MASK(i) (((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AOCSi_SHIFT(i))
159 #define ASRCSR_AICSi_MASK(i) (((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AICSi_SHIFT(i))
165 #define ASRCDRi_AICPi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICPi_SHIFT(i))
168 #define ASRCDRi_AICDi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICDi_SHIFT(i))
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/linux-5.10/drivers/mailbox/
Dimx-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
18 #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
19 #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
20 #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
24 #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
26 #define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
28 #define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
30 #define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
33 /* TX0/RX0/RXDB[0-3] */
92 iowrite32(val, priv->base + offs); in imx_mu_write()
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/linux-5.10/drivers/perf/
Dfsl_imx8_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
66 { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
67 { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
68 { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
95 u32 quirks = pmu->devtype_data->quirks; in ddr_perf_filter_cap_get()
117 int cap = (long)ea->var; in ddr_perf_filter_cap_show()
147 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in ddr_perf_cpumask_show()
169 return sprintf(page, "event=0x%02llx\n", pmu_attr->id); in ddr_pmu_event_show()
181 IMX8_DDR_PMU_EVENT_ATTR(read-accesses, 0x04),
182 IMX8_DDR_PMU_EVENT_ATTR(write-accesses, 0x05),
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