Lines Matching +full:imx8 +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0
18 #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
19 #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
20 #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
24 #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
26 #define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
28 #define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
30 #define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
33 /* TX0/RX0/RXDB[0-3] */
92 iowrite32(val, priv->base + offs); in imx_mu_write()
97 return ioread32(priv->base + offs); in imx_mu_read()
105 spin_lock_irqsave(&priv->xcr_lock, flags); in imx_mu_xcr_rmw()
106 val = imx_mu_read(priv, priv->dcfg->xCR); in imx_mu_xcr_rmw()
109 imx_mu_write(priv, val, priv->dcfg->xCR); in imx_mu_xcr_rmw()
110 spin_unlock_irqrestore(&priv->xcr_lock, flags); in imx_mu_xcr_rmw()
121 switch (cp->type) { in imx_mu_generic_tx()
123 imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]); in imx_mu_generic_tx()
124 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); in imx_mu_generic_tx()
127 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0); in imx_mu_generic_tx()
128 tasklet_schedule(&cp->txdb_tasklet); in imx_mu_generic_tx()
131 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); in imx_mu_generic_tx()
132 return -EINVAL; in imx_mu_generic_tx()
143 dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]); in imx_mu_generic_rx()
144 mbox_chan_received_data(cp->chan, (void *)&dat); in imx_mu_generic_rx()
158 switch (cp->type) { in imx_mu_scu_tx()
161 * msg->hdr.size specifies the number of u32 words while in imx_mu_scu_tx()
165 if (msg->hdr.size > sizeof(*msg) / 4) { in imx_mu_scu_tx()
170 …dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg… in imx_mu_scu_tx()
171 return -EINVAL; in imx_mu_scu_tx()
174 for (i = 0; i < 4 && i < msg->hdr.size; i++) in imx_mu_scu_tx()
175 imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]); in imx_mu_scu_tx()
176 for (; i < msg->hdr.size; i++) { in imx_mu_scu_tx()
177 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, in imx_mu_scu_tx()
182 dev_err(priv->dev, "Send data index: %d timeout\n", i); in imx_mu_scu_tx()
185 imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]); in imx_mu_scu_tx()
188 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); in imx_mu_scu_tx()
191 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); in imx_mu_scu_tx()
192 return -EINVAL; in imx_mu_scu_tx()
207 *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]); in imx_mu_scu_rx()
210 …dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg)… in imx_mu_scu_rx()
211 return -EINVAL; in imx_mu_scu_rx()
215 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr, in imx_mu_scu_rx()
218 dev_err(priv->dev, "timeout read idx %d\n", i); in imx_mu_scu_rx()
221 *data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]); in imx_mu_scu_rx()
225 mbox_chan_received_data(cp->chan, (void *)&msg); in imx_mu_scu_rx()
234 mbox_chan_txdone(cp->chan, 0); in imx_mu_txdb_tasklet()
240 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_isr()
241 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_isr()
244 ctrl = imx_mu_read(priv, priv->dcfg->xCR); in imx_mu_isr()
245 val = imx_mu_read(priv, priv->dcfg->xSR); in imx_mu_isr()
247 switch (cp->type) { in imx_mu_isr()
249 val &= IMX_MU_xSR_TEn(cp->idx) & in imx_mu_isr()
250 (ctrl & IMX_MU_xCR_TIEn(cp->idx)); in imx_mu_isr()
253 val &= IMX_MU_xSR_RFn(cp->idx) & in imx_mu_isr()
254 (ctrl & IMX_MU_xCR_RIEn(cp->idx)); in imx_mu_isr()
257 val &= IMX_MU_xSR_GIPn(cp->idx) & in imx_mu_isr()
258 (ctrl & IMX_MU_xCR_GIEn(cp->idx)); in imx_mu_isr()
267 if (val == IMX_MU_xSR_TEn(cp->idx)) { in imx_mu_isr()
268 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); in imx_mu_isr()
270 } else if (val == IMX_MU_xSR_RFn(cp->idx)) { in imx_mu_isr()
271 priv->dcfg->rx(priv, cp); in imx_mu_isr()
272 } else if (val == IMX_MU_xSR_GIPn(cp->idx)) { in imx_mu_isr()
273 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR); in imx_mu_isr()
276 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); in imx_mu_isr()
285 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_send_data()
286 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_send_data()
288 return priv->dcfg->tx(priv, cp, data); in imx_mu_send_data()
293 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_startup()
294 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_startup()
298 pm_runtime_get_sync(priv->dev); in imx_mu_startup()
299 if (cp->type == IMX_MU_TYPE_TXDB) { in imx_mu_startup()
301 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet, in imx_mu_startup()
307 if (!priv->dev->pm_domain) in imx_mu_startup()
310 ret = request_irq(priv->irq, imx_mu_isr, irq_flag, in imx_mu_startup()
311 cp->irq_desc, chan); in imx_mu_startup()
313 dev_err(priv->dev, in imx_mu_startup()
314 "Unable to acquire IRQ %d\n", priv->irq); in imx_mu_startup()
318 switch (cp->type) { in imx_mu_startup()
320 imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0); in imx_mu_startup()
323 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0); in imx_mu_startup()
334 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_shutdown()
335 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_shutdown()
337 if (cp->type == IMX_MU_TYPE_TXDB) { in imx_mu_shutdown()
338 tasklet_kill(&cp->txdb_tasklet); in imx_mu_shutdown()
339 pm_runtime_put_sync(priv->dev); in imx_mu_shutdown()
343 switch (cp->type) { in imx_mu_shutdown()
345 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); in imx_mu_shutdown()
348 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx)); in imx_mu_shutdown()
351 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx)); in imx_mu_shutdown()
357 free_irq(priv->irq, chan); in imx_mu_shutdown()
358 pm_runtime_put_sync(priv->dev); in imx_mu_shutdown()
372 if (sp->args_count != 2) { in imx_mu_scu_xlate()
373 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); in imx_mu_scu_xlate()
374 return ERR_PTR(-EINVAL); in imx_mu_scu_xlate()
377 type = sp->args[0]; /* channel type */ in imx_mu_scu_xlate()
378 idx = sp->args[1]; /* index */ in imx_mu_scu_xlate()
384 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx); in imx_mu_scu_xlate()
391 dev_err(mbox->dev, "Invalid chan type: %d\n", type); in imx_mu_scu_xlate()
392 return ERR_PTR(-EINVAL); in imx_mu_scu_xlate()
395 if (chan >= mbox->num_chans) { in imx_mu_scu_xlate()
396 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); in imx_mu_scu_xlate()
397 return ERR_PTR(-EINVAL); in imx_mu_scu_xlate()
400 return &mbox->chans[chan]; in imx_mu_scu_xlate()
408 if (sp->args_count != 2) { in imx_mu_xlate()
409 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); in imx_mu_xlate()
410 return ERR_PTR(-EINVAL); in imx_mu_xlate()
413 type = sp->args[0]; /* channel type */ in imx_mu_xlate()
414 idx = sp->args[1]; /* index */ in imx_mu_xlate()
417 if (chan >= mbox->num_chans) { in imx_mu_xlate()
418 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); in imx_mu_xlate()
419 return ERR_PTR(-EINVAL); in imx_mu_xlate()
422 return &mbox->chans[chan]; in imx_mu_xlate()
430 struct imx_mu_con_priv *cp = &priv->con_priv[i]; in imx_mu_init_generic()
432 cp->idx = i % 4; in imx_mu_init_generic()
433 cp->type = i >> 2; in imx_mu_init_generic()
434 cp->chan = &priv->mbox_chans[i]; in imx_mu_init_generic()
435 priv->mbox_chans[i].con_priv = cp; in imx_mu_init_generic()
436 snprintf(cp->irq_desc, sizeof(cp->irq_desc), in imx_mu_init_generic()
437 "imx_mu_chan[%i-%i]", cp->type, cp->idx); in imx_mu_init_generic()
440 priv->mbox.num_chans = IMX_MU_CHANS; in imx_mu_init_generic()
441 priv->mbox.of_xlate = imx_mu_xlate; in imx_mu_init_generic()
443 if (priv->side_b) in imx_mu_init_generic()
447 imx_mu_write(priv, 0, priv->dcfg->xCR); in imx_mu_init_generic()
455 struct imx_mu_con_priv *cp = &priv->con_priv[i]; in imx_mu_init_scu()
457 cp->idx = i < 2 ? 0 : i - 2; in imx_mu_init_scu()
458 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB; in imx_mu_init_scu()
459 cp->chan = &priv->mbox_chans[i]; in imx_mu_init_scu()
460 priv->mbox_chans[i].con_priv = cp; in imx_mu_init_scu()
461 snprintf(cp->irq_desc, sizeof(cp->irq_desc), in imx_mu_init_scu()
462 "imx_mu_chan[%i-%i]", cp->type, cp->idx); in imx_mu_init_scu()
465 priv->mbox.num_chans = IMX_MU_SCU_CHANS; in imx_mu_init_scu()
466 priv->mbox.of_xlate = imx_mu_scu_xlate; in imx_mu_init_scu()
469 imx_mu_write(priv, 0, priv->dcfg->xCR); in imx_mu_init_scu()
474 struct device *dev = &pdev->dev; in imx_mu_probe()
475 struct device_node *np = dev->of_node; in imx_mu_probe()
482 return -ENOMEM; in imx_mu_probe()
484 priv->dev = dev; in imx_mu_probe()
486 priv->base = devm_platform_ioremap_resource(pdev, 0); in imx_mu_probe()
487 if (IS_ERR(priv->base)) in imx_mu_probe()
488 return PTR_ERR(priv->base); in imx_mu_probe()
490 priv->irq = platform_get_irq(pdev, 0); in imx_mu_probe()
491 if (priv->irq < 0) in imx_mu_probe()
492 return priv->irq; in imx_mu_probe()
496 return -EINVAL; in imx_mu_probe()
497 priv->dcfg = dcfg; in imx_mu_probe()
499 priv->clk = devm_clk_get(dev, NULL); in imx_mu_probe()
500 if (IS_ERR(priv->clk)) { in imx_mu_probe()
501 if (PTR_ERR(priv->clk) != -ENOENT) in imx_mu_probe()
502 return PTR_ERR(priv->clk); in imx_mu_probe()
504 priv->clk = NULL; in imx_mu_probe()
507 ret = clk_prepare_enable(priv->clk); in imx_mu_probe()
509 dev_err(dev, "Failed to enable clock\n"); in imx_mu_probe()
513 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); in imx_mu_probe()
515 priv->dcfg->init(priv); in imx_mu_probe()
517 spin_lock_init(&priv->xcr_lock); in imx_mu_probe()
519 priv->mbox.dev = dev; in imx_mu_probe()
520 priv->mbox.ops = &imx_mu_ops; in imx_mu_probe()
521 priv->mbox.chans = priv->mbox_chans; in imx_mu_probe()
522 priv->mbox.txdone_irq = true; in imx_mu_probe()
526 ret = devm_mbox_controller_register(dev, &priv->mbox); in imx_mu_probe()
528 clk_disable_unprepare(priv->clk); in imx_mu_probe()
544 clk_disable_unprepare(priv->clk); in imx_mu_probe()
550 clk_disable_unprepare(priv->clk); in imx_mu_probe()
558 pm_runtime_disable(priv->dev); in imx_mu_remove()
594 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
595 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
596 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
605 if (!priv->clk) in imx_mu_suspend_noirq()
606 priv->xcr = imx_mu_read(priv, priv->dcfg->xCR); in imx_mu_suspend_noirq()
623 if (!imx_mu_read(priv, priv->dcfg->xCR) && !priv->clk) in imx_mu_resume_noirq()
624 imx_mu_write(priv, priv->xcr, priv->dcfg->xCR); in imx_mu_resume_noirq()
633 clk_disable_unprepare(priv->clk); in imx_mu_runtime_suspend()
643 ret = clk_prepare_enable(priv->clk); in imx_mu_runtime_resume()
645 dev_err(dev, "failed to enable clock\n"); in imx_mu_runtime_resume()