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Searched +full:hi3620 +full:- +full:clock (Results 1 – 7 of 7) sorted by relevance

/linux-5.10/Documentation/devicetree/bindings/clock/
Dhi3620-clock.txt1 * Hisilicon Hi3620 Clock Controller
3 The Hi3620 clock controller generates and supplies clock to various
4 controllers within the Hi3620 SoC.
8 - compatible: should be one of the following.
9 - "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC.
10 - "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc.
12 - reg: physical base address of the controller and length of memory mapped
15 - #clock-cells: should be 1.
17 Each clock is assigned an identifier and client nodes use this identifier
18 to specify the clock which they consume.
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/linux-5.10/arch/arm/boot/dts/
Dhi3620.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hisilicon Ltd. Hi3620 SoC
5 * Copyright (C) 2012-2013 Hisilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
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/linux-5.10/drivers/clk/hisilicon/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Hisilicon Clock specific Makefile
6 obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o clk-hisi-phase.o
8 obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
9 obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
10 obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
11 obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
12 obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
13 obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
14 obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o
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Dclk-hi3620.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Hisilicon Hi3620 clock driver
5 * Copyright (c) 2012-2013 Hisilicon Limited.
6 * Copyright (c) 2012-2013 Linaro Limited.
13 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/hi3620-clock.h>
24 /* clock parent list */
217 CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);
286 if ((req->rate <= 13000000) && (mclk->id == HI3620_MMC_CIUCLK1)) { in mmc_clk_determine_rate()
287 req->rate = 13000000; in mmc_clk_determine_rate()
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Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Hisilicon Hi3620 clock gate driver
5 * Copyright (c) 2012-2013 Hisilicon Limited.
6 * Copyright (c) 2012-2013 Linaro Limited.
15 #include <linux/clk-provider.h>
142 struct clk **clocks = data->clk_data.clks; \
/linux-5.10/Documentation/devicetree/bindings/mmc/
Dk3-dw-mshc.txt4 Read synopsys-dw-mshc.txt for more details
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
22 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
26 /* for Hi3620 */
30 compatible = "hisilicon,hi4511-dw-mshc";
33 #address-cells = <1>;
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/linux-5.10/Documentation/devicetree/bindings/arm/hisilicon/controller/
Dsysctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wei Xu <xuwei5@hisilicon.com>
23 Hisilicon system controller --> hisilicon,sysctrl
24 HiP01 system controller --> hisilicon,hip01-sysctrl
25 Hi6220 system controller --> hisilicon,hi6220-sysctrl
26 Hi3519 system controller --> hisilicon,hi3519-sysctrl
29 - if:
33 const: hisilicon,hi6220-sysctrl
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