1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Hisilicon Hi3620 clock driver
5  * Copyright (c) 2012-2013 Hisilicon Limited.
6  * Copyright (c) 2012-2013 Linaro Limited.
13 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/hi3620-clock.h>
24 /* clock parent list */
217 CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);
286 	if ((req->rate <= 13000000) && (mclk->id == HI3620_MMC_CIUCLK1)) {  in mmc_clk_determine_rate()
287 		req->rate = 13000000;  in mmc_clk_determine_rate()
288 		req->best_parent_rate = 26000000;  in mmc_clk_determine_rate()
289 	} else if (req->rate <= 26000000) {  in mmc_clk_determine_rate()
290 		req->rate = 25000000;  in mmc_clk_determine_rate()
291 		req->best_parent_rate = 180000000;  in mmc_clk_determine_rate()
292 	} else if (req->rate <= 52000000) {  in mmc_clk_determine_rate()
293 		req->rate = 50000000;  in mmc_clk_determine_rate()
294 		req->best_parent_rate = 360000000;  in mmc_clk_determine_rate()
295 	} else if (req->rate <= 100000000) {  in mmc_clk_determine_rate()
296 		req->rate = 100000000;  in mmc_clk_determine_rate()
297 		req->best_parent_rate = 720000000;  in mmc_clk_determine_rate()
300 		req->rate = 180000000;  in mmc_clk_determine_rate()
301 		req->best_parent_rate = 1440000000;  in mmc_clk_determine_rate()
303 	return -EINVAL;  in mmc_clk_determine_rate()
355 		return -EINVAL;  in mmc_clk_set_timing()
360 	val = readl_relaxed(mclk->clken_reg);  in mmc_clk_set_timing()
361 	val &= ~(1 << mclk->clken_bit);  in mmc_clk_set_timing()
362 	writel_relaxed(val, mclk->clken_reg);  in mmc_clk_set_timing()
364 	val = readl_relaxed(mclk->sam_reg);  in mmc_clk_set_timing()
365 	val = mmc_clk_delay(val, sam, mclk->sam_off, mclk->sam_bits);  in mmc_clk_set_timing()
366 	writel_relaxed(val, mclk->sam_reg);  in mmc_clk_set_timing()
368 	val = readl_relaxed(mclk->drv_reg);  in mmc_clk_set_timing()
369 	val = mmc_clk_delay(val, drv, mclk->drv_off, mclk->drv_bits);  in mmc_clk_set_timing()
370 	writel_relaxed(val, mclk->drv_reg);  in mmc_clk_set_timing()
372 	val = readl_relaxed(mclk->div_reg);  in mmc_clk_set_timing()
373 	val = mmc_clk_delay(val, div, mclk->div_off, mclk->div_bits);  in mmc_clk_set_timing()
374 	writel_relaxed(val, mclk->div_reg);  in mmc_clk_set_timing()
376 	val = readl_relaxed(mclk->clken_reg);  in mmc_clk_set_timing()
377 	val |= 1 << mclk->clken_bit;  in mmc_clk_set_timing()
378 	writel_relaxed(val, mclk->clken_reg);  in mmc_clk_set_timing()
390 	if (mclk->id == HI3620_MMC_CIUCLK1)  in mmc_clk_prepare()
420 		return ERR_PTR(-ENOMEM);  in hisi_register_clk_mmc()
422 	init.name = mmc_clk->name;  in hisi_register_clk_mmc()
424 	init.flags = mmc_clk->flags;  in hisi_register_clk_mmc()
425 	init.parent_names = (mmc_clk->parent_name ? &mmc_clk->parent_name : NULL);  in hisi_register_clk_mmc()
426 	init.num_parents = (mmc_clk->parent_name ? 1 : 0);  in hisi_register_clk_mmc()
427 	mclk->hw.init = &init;  in hisi_register_clk_mmc()
429 	mclk->id = mmc_clk->id;  in hisi_register_clk_mmc()
430 	mclk->clken_reg = base + mmc_clk->clken_reg;  in hisi_register_clk_mmc()
431 	mclk->clken_bit = mmc_clk->clken_bit;  in hisi_register_clk_mmc()
432 	mclk->div_reg = base + mmc_clk->div_reg;  in hisi_register_clk_mmc()
433 	mclk->div_off = mmc_clk->div_off;  in hisi_register_clk_mmc()
434 	mclk->div_bits = mmc_clk->div_bits;  in hisi_register_clk_mmc()
435 	mclk->drv_reg = base + mmc_clk->drv_reg;  in hisi_register_clk_mmc()
436 	mclk->drv_off = mmc_clk->drv_off;  in hisi_register_clk_mmc()
437 	mclk->drv_bits = mmc_clk->drv_bits;  in hisi_register_clk_mmc()
438 	mclk->sam_reg = base + mmc_clk->sam_reg;  in hisi_register_clk_mmc()
439 	mclk->sam_off = mmc_clk->sam_off;  in hisi_register_clk_mmc()
440 	mclk->sam_bits = mmc_clk->sam_bits;  in hisi_register_clk_mmc()
442 	clk = clk_register(NULL, &mclk->hw);  in hisi_register_clk_mmc()
469 	clk_data->clks = kcalloc(num, sizeof(*clk_data->clks), GFP_KERNEL);  in hi3620_mmc_clk_init()
470 	if (!clk_data->clks)  in hi3620_mmc_clk_init()
475 		clk_data->clks[mmc_clk->id] =  in hi3620_mmc_clk_init()
479 	clk_data->clk_num = num;  in hi3620_mmc_clk_init()
483 CLK_OF_DECLARE(hi3620_mmc_clk, "hisilicon,hi3620-mmc-clock", hi3620_mmc_clk_init);