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/linux/arch/riscv/kernel/
H A Dsbi.c80 * sbi_shutdown() - Remove all the harts from executing supervisor code.
394 * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
395 * @cpu_mask: A cpu mask containing all the target harts.
408 * remote harts for a virtual address range belonging to a specific ASID or not.
410 * @cpu_mask: A cpu mask containing all the target harts.
434 * harts for the specified guest physical address range.
435 * @cpu_mask: A cpu mask containing all the target harts.
452 * remote harts for a guest physical address range belonging to a specific VMID.
454 * @cpu_mask: A cpu mask containing all the target harts.
473 * harts for the current guest virtual address range.
[all …]
H A Dcpu.c343 * denominator of extensions supported across all harts. A true list of in c_show()
367 * additional extensions not present across all harts. in c_show()
H A Dsys_hwprobe.c266 * extensions are supported on all harts, and only supports the in hwprobe_one_pair()
498 * all harts, then assume all CPUs are the same, and allow the vDSO to in init_hwprobe_vdso_data()
H A Dcpufeature.c1009 * All "okay" harts should have same isa. Set HWCAP based on in riscv_fill_hwcap_from_ext_list()
1126 pr_warn("Zicboz disabled as it is unavailable on some harts\n"); in riscv_user_isa_enable()
1131 pr_warn("Zicbom disabled as it is unavailable on some harts\n"); in riscv_user_isa_enable()
1135 pr_warn("Zicbop disabled as it is unavailable on some harts\n"); in riscv_user_isa_enable()
H A Dhead.S181 * - have too many harts on CONFIG_RISCV_BOOT_SPINWAIT
H A Dprocess.c407 * Assume the supported PMLEN values are the same on all harts. in tagged_addr_init()
/linux/Documentation/devicetree/bindings/timer/
H A Dandestech,plmt0.yaml11 functionality for a set of HARTs on a RISC-V platform. It has a single
33 Specifies which harts are connected to the PLMT0. Each item must points
35 PLMT0 supports 1 hart up to 32 harts.
/linux/drivers/acpi/riscv/
H A Drhct.c107 pr_warn("CBOM size is not the same across harts\n"); in acpi_parse_hart_info_cmo_node()
114 pr_warn("CBOZ size is not the same across harts\n"); in acpi_parse_hart_info_cmo_node()
121 pr_warn("CBOP size is not the same across harts\n"); in acpi_parse_hart_info_cmo_node()
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,imsics.yaml22 which is same for given privilege level across CPUs (or HARTs).
26 IMSIC interrupt files at that privilege level across CPUs (or HARTs).
73 This property represents the set of CPUs (or HARTs) for which given
H A Driscv,aplic.yaml46 RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
122 // Example 1 (APLIC domains directly injecting interrupt to HARTs):
H A Dandestech,plicsw.yaml35 Specifies which harts are connected to the PLIC_SW. Each item must points
H A Dthead,c900-aclint-sswi.yaml14 supervisor-level IPI functionality for a set of HARTs on a supported
H A Driscv,cpu-intc.yaml31 present HARTs in the system.
H A Dsifive,plic-1.0.0.yaml18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
/linux/Documentation/arch/riscv/
H A Dboot.rst68 - ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kernel, one hart
69 wins a lottery and executes the early boot code while the other harts are
73 initialization phase and then will start all other harts using the SBI HSM
/linux/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml24 having four harts.
116 thead systems where the vector register length is not identical on all harts, or
/linux/tools/testing/selftests/riscv/hwprobe/
H A Dcbo.c183 ksft_exit_fail_msg("%s is only present on a subset of harts.\n" in check_no_zicbo_cpus()
184 "Use taskset to select a set of harts where %s\n" in check_no_zicbo_cpus()
/linux/arch/csky/abiv2/
H A Dcacheflush.c81 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm_range()
/linux/drivers/irqchip/
H A Dirq-riscv-imsic-state.h50 /* Global configuration common for all HARTs */
/linux/Documentation/devicetree/bindings/iommu/
H A Driscv,iommu.yaml63 RISC-V HARTS. The cause to interrupt vector is software defined
/linux/drivers/clocksource/
H A Dtimer-riscv.c80 * It is guaranteed that all the timers across all the harts are synchronized
/linux/arch/riscv/kvm/
H A Daia.c596 * run on other HARTs in kvm_riscv_aia_disable()
/linux/drivers/perf/
H A Driscv_pmu_sbi.c90 * RISC-V doesn't have heterogeneous harts yet. This need to be part of
91 * per_cpu in case of harts with different pmu counters
/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml55 On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific