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/linux-6.15/Documentation/devicetree/bindings/mailbox/
Dmicrochip,sbi-ipc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Inter-processor communication (IPC) mailbox controller
10 - Valentina Fernandez <valentina.fernandezalanis@microchip.com>
13 The Microchip Inter-processor Communication (IPC) facilitates
20 - description:
22 mode (s-mode). This SBI interface is compatible with the Mi-V
23 Inter-hart Communication (IHC) IP.
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/linux-6.15/Documentation/devicetree/bindings/iio/addac/
Dadi,ad74115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74115H is a single-channel software configurable input/output
17 chip solution with an SPI interface. The device features a 16-bit ADC and a
18 14-bit DAC.
25 - adi,ad74115h
30 spi-max-frequency:
33 spi-cpol: true
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Dadi,ad74413r.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74412R and AD74413R are quad-channel software configurable input/output
18 The devices feature a 16-bit ADC and four configurable 13-bit DACs to provide
20 The AD74413R differentiates itself from the AD74412R by being HART-compatible.
27 - adi,ad74412r
28 - adi,ad74413r
33 '#address-cells':
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/linux-6.15/arch/riscv/kernel/
Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
27 * Returns the hart ID of the given device tree node, or -ENODEV if the node
28 * isn't an enabled and valid RISC-V hart node.
30 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_of_processor_hartid() argument
34 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_of_processor_hartid()
35 if (*hart == ~0UL) { in riscv_of_processor_hartid()
36 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hartid()
37 return -ENODEV; in riscv_of_processor_hartid()
40 cpu = riscv_hartid_to_cpuid(*hart); in riscv_of_processor_hartid()
45 return -ENODEV; in riscv_of_processor_hartid()
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Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include <asm/asm-offsets.h>
18 #include "efi-header.S"
23 * Image header expected by Linux boot-loaders. The image header data
32 c.li s4,-13
42 /* Image load offset (0MB) from start of RAM for M-mode */
46 /* Image load offset(2MB) from start of RAM */
54 .dword _end - _start
63 .word pe_head_start - _start
71 .align 2
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Dkexec_relocate.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019 FORTH-ICS/CARV
19 * s3: (const) The hartid of the current hart
50 * With C-extension, here we get 42 Bytes and the next
57 .align 2
59 REG_L t0, 0(s0) /* t0 = *image->entry */
60 addi s0, s0, RISCV_SZPTR /* image->entry++ */
62 /* IND_DESTINATION entry ? -> save destination address */
64 beqz t1, 2f
68 2:
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/linux-6.15/arch/riscv/mm/
Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0-only
25 if (num_online_cpus() < 2) in flush_icache_all()
35 * Performs an icache flush for the given MM context. RISC-V has no direct
39 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
42 * execution resumes on each hart.
51 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm()
52 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
54 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm()
65 if (mm == current->active_mm && local) { in flush_icache_mm()
68 * performed on this hart between setting a hart's cpumask bit in flush_icache_mm()
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Dcontext.c1 // SPDX-License-Identifier: GPL-2.0
87 /* Mark ASID #0 as used because it is used at boot-time */ in __flush_context()
90 /* Queue a TLB invalidation for each CPU on next context-switch */ in __flush_context()
97 unsigned long cntx = atomic_long_read(&mm->context.id); in __new_context()
115 * re-use it if possible. in __new_context()
150 cntx = atomic_long_read(&mm->context.id); in set_mm_asid()
153 * If our active_context is non-zero and the context matches the in set_mm_asid()
159 * - We get a zero back from the cmpxchg and end up waiting on the in set_mm_asid()
163 * - We get a valid context back from the cmpxchg then we continue in set_mm_asid()
178 cntx = atomic_long_read(&mm->context.id); in set_mm_asid()
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/linux-6.15/Documentation/devicetree/bindings/interrupt-controller/
Driscv,imsics.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Incoming MSI Controller (IMSIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
15 AIA specification can be found at https://github.com/riscv/riscv-aia.
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
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Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
13 to the core. Every interrupt is ultimately routed through a hart's HLIC
14 before it interrupts that hart.
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
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Driscv,aplic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
10 - Anup Patel <anup@brainfault.org>
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
15 in a RISC-V platform. The RISC-V AIA specification can be found at
16 https://github.com/riscv/riscv-aia.
18 The RISC-V APLIC is implemented as hierarchical APLIC domains where all
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Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
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Dthead,c900-aclint-sswi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: T-HEAD C900 ACLINT Supervisor-level Software Interrupt Device
10 - Inochi Amaoto <inochiama@outlook.com>
14 supervisor-level IPI functionality for a set of HARTs on a THEAD
16 HART connected to the SSWI device.
21 - enum:
22 - sophgo,sg2044-aclint-sswi
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/linux-6.15/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
18 hart: A hardware execution context, which contains all the state
19 mandated by the RISC-V ISA: a PC and some registers. This
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Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
18 This document defines properties that indicate whether a hart supports a
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/linux-6.15/drivers/mailbox/
Dmailbox-mchp-ipc-sbi.c1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip Inter-Processor communication (IPC) driver
5 * Copyright (c) 2021 - 2024 Microchip Technology Inc. All rights reserved.
19 #include <linux/dma-mapping.h>
21 #include <linux/mailbox/mchp-ipc.h>
44 * struct mchp_ipc_mbox_info - IPC probe message format
58 * struct mchp_ipc_init - IPC channel init message format
70 * struct mchp_ipc_status - IPC status message format
85 * struct mchp_ipc_sbi_msg - IPC SBI payload message
150 struct mchp_ipc_sbi_chan *chan_info = (struct mchp_ipc_sbi_chan *)chan->con_priv; in mchp_ipc_prepare_receive_req()
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/linux-6.15/tools/arch/riscv/include/uapi/asm/
Dunistd.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
6 * it under the terms of the GNU General Public License version 2 as
23 #include <asm-generic/unistd.h>
26 * Allows the instruction cache to be flushed from userspace. Despite RISC-V
29 * kernel might schedule a process on another hart. There is no way for
31 * thread->hart mappings), so we've defined a RISC-V specific system call to
/linux-6.15/drivers/irqchip/
Dirq-riscv-aplic-msi.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/irqchip/riscv-aplic.h>
13 #include <linux/irqchip/riscv-imsic.h>
21 #include "irq-riscv-aplic-main.h"
43 * The section "4.9.2 Special consideration for level-sensitive interrupt in aplic_msi_irq_retrigger_level()
44 * sources" of the RISC-V AIA specification says: in aplic_msi_irq_retrigger_level()
52 writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); in aplic_msi_irq_retrigger_level()
60 * EOI handling is required only for level-triggered interrupts in aplic_msi_irq_eoi()
73 * Updating sourcecfg register for level-triggered interrupts in aplic_msi_irq_set_type()
84 struct aplic_msicfg *mc = &priv->msicfg; in aplic_msi_write_msg()
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Dirq-riscv-imsic-state.c1 // SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "riscv-imsic: " fmt
22 #include "irq-riscv-imsic-state.h"
63 return imsic ? &imsic->global : NULL; in imsic_get_global_config()
74 imask = BIT(id & (__riscv_xlen - 1)); in __imsic_eix_read_clear()
102 * are XLEN-wide and we must not touch IDs which in __imsic_eix_update()
106 for (i = id & (__riscv_xlen - 1); id < last_id && i < __riscv_xlen; i++) { in __imsic_eix_update()
134 lockdep_assert_held(&lpriv->lock); in __imsic_local_sync()
136 for_each_set_bit(i, lpriv->dirty_bitmap, imsic->global.nr_ids + 1) { in __imsic_local_sync()
139 vec = &lpriv->vectors[i]; in __imsic_local_sync()
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/linux-6.15/tools/testing/selftests/futex/include/
Dlogging.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * Darren Hart <dvhart@linux.intel.com>
13 * 2009-Nov-6: Initial version by Darren Hart <dvhart@linux.intel.com>
32 #define GREEN '3', '2'
58 #define VINFO 2
64 #define RET_ERROR -1
65 #define RET_FAIL -2
68 * log_color() - Use colored output for PASS, ERROR, and FAIL strings
85 * log_verbosity() - Set verbosity of test output
101 * print_result() - Print standard PASS | ERROR | FAIL results
/linux-6.15/tools/testing/selftests/futex/functional/
Dfutex_requeue_pi_mismatched_ops.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * 2. Attempt to use FUTEX_CMP_REQUEUE_PI on the futex from 1.
9 * 3. The kernel must detect the mismatch and return -EINVAL.
12 * Darren Hart <dvhart@linux.intel.com>
15 * 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
29 #define TEST_NAME "futex-requeue-pi-mismatched-ops"
38 printf(" -c Use color\n"); in usage()
39 printf(" -h Display this help message\n"); in usage()
40 printf(" -v L Verbosity level: %d=QUIET %d=CRITICAL %d=INFO\n", in usage()
48 child_ret = -errno; in blocking_child()
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Dfutex_wait_timeout.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Darren Hart <dvhart@linux.intel.com>
13 * 2009-Nov-6: Initial version by Darren Hart <dvhart@linux.intel.com>
14 * 2021-Apr-26: More test cases by André Almeida <andrealmeid@collabora.com>
23 #define TEST_NAME "futex-wait-timeout"
32 printf(" -c Use color\n"); in usage()
33 printf(" -h Display this help message\n"); in usage()
34 printf(" -t N Timeout in nanoseconds (default: 100,000)\n"); in usage()
35 printf(" -v L Verbosity level: %d=QUIET %d=CRITICAL %d=INFO\n", in usage()
86 to->tv_nsec += timeout_ns; in futex_get_abs_timeout()
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/linux-6.15/arch/riscv/purgatory/
Dentry.S1 /* SPDX-License-Identifier: GPL-2.0-only */
15 .align 2
19 mv s0, a0 /* The hartid of the current hart */
/linux-6.15/Documentation/arch/riscv/
Dboot.rst1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
32 The RISC-V kernel expects:
37 -------------------------------------
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/linux-6.15/Documentation/devicetree/bindings/cpu/
Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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