riscv/mm/context.c

1 // SPDX-License-Identifier: GPL-2.0
87 	/* Mark ASID #0 as used because it is used at boot-time */  in __flush_context()
90 	/* Queue a TLB invalidation for each CPU on next context-switch */  in __flush_context()
97 	unsigned long cntx = atomic_long_read(&mm->context.id);  in __new_context()
115 		 * re-use it if possible.  in __new_context()
150 	cntx = atomic_long_read(&mm->context.id);  in set_mm_asid()
153 	 * If our active_context is non-zero and the context matches the  in set_mm_asid()
159 	 * - We get a zero back from the cmpxchg and end up waiting on the  in set_mm_asid()
163 	 * - We get a valid context back from the cmpxchg then we continue  in set_mm_asid()
178 	cntx = atomic_long_read(&mm->context.id);  in set_mm_asid()
181 		atomic_long_set(&mm->context.id, cntx);  in set_mm_asid()
192 	csr_write(CSR_SATP, virt_to_pfn(mm->pgd) |  in set_mm_asid()
203 	csr_write(CSR_SATP, virt_to_pfn(mm->pgd) | satp_mode);  in set_mm_noasid()
231 	/* Figure-out number of ASID bits in HW */  in asids_init()
241 	 * we polluted the TLB of current HART so let's do TLB flushed  in asids_init()
246 	/* Pre-compute ASID details */  in asids_init()
253 	 * at-least twice more than CPUs  in asids_init()
255 	if (num_asids > (2 * num_possible_cpus())) {  in asids_init()
286  * on the local CPU.  RISC-V has no direct mechanism for instruction cache
289  * behavior in a common case (a bunch of single-hart processes on a many-hart
290  * machine, ie 'make -j') we avoid the IPIs for harts that are not currently
292  * cache flush to be performed before execution resumes on each hart.  This
294  * refers to the current hart.
302 	if (cpumask_test_and_clear_cpu(cpu, &mm->context.icache_stale_mask)) {  in flush_icache_deferred()
304 		 * Ensure the remote hart's writes are visible to this hart.  in flush_icache_deferred()