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/qemu/hw/vfio/
H A Dpci-quirks.h20 * vfio_generic_window_address_quirk handles the address register and
21 * vfio_generic_window_data_quirk handles the data register. These ops
56 * The generic mirror quirk handles devices which expose PCI config space
/qemu/include/io/
H A Dchannel.h211 * @fds: pointer to an array that will received file handles
259 * @fds: an array of file handles to send
260 * @nfds: number of file handles in @fds
277 * array should be non-NULL and provide the handles.
387 * receiving of file handles.
402 * sending of file handles.
417 * receiving of file handles, and only supports reading into
433 * sending of file handles, and only supports writing from a
559 * sending of file handles as well as beginning the write at the
595 * receiving of file handles as well as beginning the read at the
[all …]
/qemu/docs/specs/
H A Dppc-xive.rst29 Controller (VC). It handles event coalescing and perform interrupt
34 thread and handles the delivery of the external interrupt to the
173 The O/S handles the interrupt and when done, performs an EOI using a
180 handles the source ESBs and the MMIO interface to control them.
H A Dacpi_hw_reduced_hotplug.rst6 specific device introduced in ACPI v6.1 that handles all platform
/qemu/qga/
H A Dvss-win32.h16 #include "qga/vss-win32/vss-handles.h"
/qemu/qga/vss-win32/
H A Dvss-debug.h14 #include <vss-handles.h>
H A Dvss-common.h50 #include "vss-handles.h"
/qemu/python/
H A Dsetup.cfg145 too-many-function-args, # mypy handles this with less false positives.
147 no-member, # mypy also handles this better.
/qemu/include/migration/
H A Dcolo.h41 * Handles change of x-checkpoint-delay migration parameter, called from
/qemu/include/crypto/
H A Drandom.h44 * Initializes the handles used by qcrypto_random_bytes
/qemu/hw/cxl/
H A Dcxl-events.c215 * "The device shall verify the event record handles specified in the input in cxl_event_clear_records()
226 /* NOTE: Both handles are little endian. */ in cxl_event_clear_records()
/qemu/include/system/
H A Ddump.h79 uint32_t current_cpu; /* CPU# which handles dump */
97 uint32_t current_cpu; /* CPU# which handles dump */
/qemu/target/arm/tcg/
H A Dtlb-insns.c391 * Currently handles both VAE2 and VALE2, since we don't support in tlbi_aa64_vae2_write()
407 * Currently handles both VAE3 and VALE3, since we don't support in tlbi_aa64_vae3_write()
433 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, in tlbi_aa64_vae1_write()
899 * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, in tlbi_aa64_rvae1_write()
914 * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, in tlbi_aa64_rvae1is_write()
929 * Currently handles all of RVAE2 and RVALE2, in tlbi_aa64_rvae2_write()
946 * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS, in tlbi_aa64_rvae2is_write()
961 * Currently handles all of RVAE3 and RVALE3, in tlbi_aa64_rvae3_write()
975 * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS, in tlbi_aa64_rvae3is_write()
/qemu/hw/xenpv/
H A Dxen_machine_pv.c41 /* nothing to do, libxl handles everything */ in xen_init_pv()
/qemu/linux-user/s390x/
H A Dvdso.ld19 * QEMU handles syscall restart internally, so we don't
/qemu/include/standard-headers/linux/
H A Dvirtio_net.h35 #define VIRTIO_NET_F_CSUM 0 /* Host handles pkts w/ partial csum */
36 #define VIRTIO_NET_F_GUEST_CSUM 1 /* Guest handles pkts w/ partial csum */
75 #define VIRTIO_NET_F_GSO 6 /* Host handles pkts w/ any GSO type */
/qemu/linux-user/hppa/
H A Dvdso.ld27 * QEMU handles syscall restart internally, so we don't
/qemu/hw/misc/
H A Darm_integrator_debug.c5 * ensures something other than unassigned_mem_read() handles access
/qemu/hw/acpi/
H A Dhmat.c190 * Number of SMBIOS handles (n) in build_hmat_cache()
192 * without SMBIOS entries for now, so set Number of SMBIOS handles in build_hmat_cache()
/qemu/hw/xen/
H A Dxen_pt_load_rom.c28 /* If loading ROM from file, pci handles it */ in pci_assign_dev_load_option_rom()
/qemu/hw/remote/
H A Diommu.c24 * - Each TYPE_VFIO_USER_SERVER instance handles one PCIDevice on a PCIBus.
/qemu/scripts/
H A Dmake-release67 # don't necessarily have much control over how a submodule handles its
/qemu/hw/core/
H A Dsysbus-fdt.c342 error_report("%s clocks property should contain 2 handles", __func__); in add_amd_xgbe_fdt_node()
350 * clock handles fetched from host dt are in be32 layout whereas in add_amd_xgbe_fdt_node()
351 * rest of the code uses cpu layout. Also guest clock handles are in add_amd_xgbe_fdt_node()
/qemu/include/hw/acpi/
H A Dgeneric_event_device.h12 * device[ACPI v6.1 Section 5.6.9] that handles all platform events,
/qemu/plugins/
H A Dapi.c392 * Create register handles.
400 * We also construct a result array with those handles and some

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