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/qemu/tests/qtest/
H A Dnpcm7xx_gpio-test.c2 * QTest testcase for the Nuvoton NPCM7xx GPIO modules.
21 #define GPIO(x) (0xf0010000 + (x) * 0x1000) macro
24 /* GPIO registers */
58 if (readl(GPIO(n) + GP_N_TLOCK1) != 0) { in gpio_unlock()
59 writel(GPIO(n) + GP_N_TLOCK2, 0xc0de1248); in gpio_unlock()
60 writel(GPIO(n) + GP_N_TLOCK1, 0xc0defa73); in gpio_unlock()
64 /* Restore the GPIO controller to a sensible default state. */
69 writel(GPIO(n) + GP_N_EVEN, 0x00000000); in gpio_reset()
70 writel(GPIO(n) + GP_N_EVST, 0xffffffff); in gpio_reset()
71 writel(GPIO(n) + GP_N_POL, 0x00000000); in gpio_reset()
[all …]
H A Dstm32l4x5_gpio-test.c94 static uint32_t gpio_readl(unsigned int gpio, unsigned int offset) in gpio_readl() argument
96 return readl(gpio + offset); in gpio_readl()
99 static void gpio_writel(unsigned int gpio, unsigned int offset, uint32_t value) in gpio_writel() argument
101 writel(gpio + offset, value); in gpio_writel()
104 static void gpio_set_bit(unsigned int gpio, unsigned int reg, in gpio_set_bit() argument
108 gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << pin); in gpio_set_bit()
111 static void gpio_set_2bits(unsigned int gpio, unsigned int reg, in gpio_set_2bits() argument
116 gpio_writel(gpio, reg, (gpio_readl(gpio, reg) & mask) | value << offset); in gpio_set_2bits()
124 static void gpio_set_irq(unsigned int gpio, int num, int level) in gpio_set_irq() argument
126 g_autofree char *name = g_strdup_printf("/machine/soc/gpio%c", in gpio_set_irq()
[all …]
H A Daspeed_gpio-test.c2 * QTest testcase for the Aspeed GPIO Controller.
44 qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV4", true); in test_set_colocated_pins()
45 qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV5", false); in test_set_colocated_pins()
46 qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV6", true); in test_set_colocated_pins()
47 qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV7", false); in test_set_colocated_pins()
48 g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV4")); in test_set_colocated_pins()
49 g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV5")); in test_set_colocated_pins()
50 g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV6")); in test_set_colocated_pins()
51 g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV7")); in test_set_colocated_pins()
63 sprintf(name, "gpio%c%d", c, i); in test_set_input_pins()
[all …]
H A Dast2700-gpio-test.c2 * QTest testcase for the ASPEED AST2700 GPIO Controller.
54 sprintf(name, "gpio%c%d", c, i); in test_input_pins()
60 qtest_qom_set_bool(s, "/machine/soc/gpio", name, true); in test_input_pins()
65 qtest_qom_set_bool(s, "/machine/soc/gpio", name, false); in test_input_pins()
91 qtest_add_func("/ast2700/gpio/input_pins", test_2700_input_pins); in main()
92 qtest_add_func("/ast2700/gpio/output_pins", test_2700_output_pins); in main()
/qemu/tests/qtest/libqos/
H A Dvirtio-gpio.c2 * virtio-gpio nodes for testing
14 #include "virtio-gpio.h"
18 static void virtio_gpio_cleanup(QVhostUserGPIO *gpio) in virtio_gpio_cleanup() argument
20 QVirtioDevice *vdev = gpio->vdev; in virtio_gpio_cleanup()
24 qvirtqueue_cleanup(vdev->bus, gpio->queues[i], alloc); in virtio_gpio_cleanup()
26 g_free(gpio->queues); in virtio_gpio_cleanup()
34 static void virtio_gpio_setup(QVhostUserGPIO *gpio) in virtio_gpio_setup() argument
36 QVirtioDevice *vdev = gpio->vdev; in virtio_gpio_setup()
44 gpio->queues = g_new(QVirtQueue *, 2); in virtio_gpio_setup()
46 gpio->queues[i] = qvirtqueue_setup(vdev, alloc, i); in virtio_gpio_setup()
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/qemu/include/hw/misc/
H A Diotkit-secctl.h19 * + named GPIO output "sec_resp_cfg" indicating whether blocked accesses
21 * + named GPIO output "nsc_cfg" whose value tracks the NSCCFG register value
22 * + named GPIO output "msc_irq" for the combined IRQ line from the MSCs
24 * + named GPIO outputs apb_ppc0_nonsec[0..2] and apb_ppc1_nonsec
25 * + named GPIO outputs apb_ppc0_ap[0..2] and apb_ppc1_ap
26 * + named GPIO outputs apb_ppc{0,1}_irq_enable
27 * + named GPIO outputs apb_ppc{0,1}_irq_clear
28 * + named GPIO inputs apb_ppc{0,1}_irq_status
31 * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
32 * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
[all …]
H A Dled.h48 * Determines whether a GPIO is using a positive (active-high)
49 * logic (when used with GPIO, the intensity at reset is related
50 * to the GPIO polarity).
77 * This utility is meant for LED connected to GPIO.
84 * @gpio_polarity: GPIO polarity
H A Dtz-ppc.h50 * + Named GPIO inputs "cfg_nonsec[0..15]": set to 1 if the port should be
52 * + Named GPIO inputs "cfg_ap[0..15]": set to 1 if the port should be
54 * + Named GPIO input "cfg_sec_resp": set to 1 if a rejected transaction should
56 * + Named GPIO input "irq_enable": set to 1 to enable interrupts
57 * + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt
58 * + Named GPIO output "irq": set for a transaction-failed interrupt
H A Dtz-msc.h29 * We don't currently implement the irq_enable GPIO input, because on
34 * + Named GPIO input "cfg_nonsec": set to 1 if the bus master should be
36 * + Named GPIO input "cfg_sec_resp": set to 1 if a rejected transaction should
38 * + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt
39 * + Named GPIO output "irq": set for a transaction-failed interrupt
/qemu/hw/misc/macio/
H A Dgpio.c2 * PowerMac NewWorld MacIO GPIO emulation
30 #include "hw/misc/macio/gpio.h"
43 void macio_set_gpio(MacIOGPIOState *s, uint32_t gpio, bool state) in macio_set_gpio() argument
47 trace_macio_set_gpio(gpio, state); in macio_set_gpio()
49 if (s->gpio_regs[gpio] & OUT_ENABLE) { in macio_set_gpio()
51 "GPIO: Setting GPIO %d while it's an output\n", gpio); in macio_set_gpio()
54 new_reg = s->gpio_regs[gpio] & ~IN_DATA; in macio_set_gpio()
59 if (new_reg == s->gpio_regs[gpio]) { in macio_set_gpio()
63 s->gpio_regs[gpio] = new_reg; in macio_set_gpio()
72 switch (gpio) { in macio_set_gpio()
[all …]
H A Dtrace-events17 # gpio.c
18 macio_set_gpio(int gpio, bool state) "setting GPIO %d to %d"
19 macio_gpio_irq_assert(int gpio) "asserting GPIO %d"
20 macio_gpio_irq_deassert(int gpio) "deasserting GPIO %d"
/qemu/include/hw/
H A Dqdev-core.h593 * typedef GpioPolarity - Polarity of a GPIO line
595 * GPIO lines use either positive (active-high) logic,
609 * qdev_get_gpio_in: Get one of a device's anonymous input GPIO lines
610 * @dev: Device whose GPIO we want
611 * @n: Number of the anonymous GPIO line (which must be in range)
613 * Returns the qemu_irq corresponding to an anonymous input GPIO line
615 * @n of the GPIO line must be valid (i.e. be at least 0 and less than
620 * device models to wire up the GPIO lines; usually the return value
622 * connect another device's output GPIO line to this input.
624 * For named input GPIO lines, use qdev_get_gpio_in_named().
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/qemu/hw/gpio/
H A Dtrace-events23 …escription, unsigned id, unsigned prev_state, unsigned current_state) "%s GPIO id:%u status: %u ->…
27 pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
28 pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
45 stm32l4x5_gpio_read(char *gpio, uint64_t addr) "GPIO%s addr: 0x%" PRIx64 " "
46 stm32l4x5_gpio_write(char *gpio, uint64_t addr, uint64_t data) "GPIO%s addr: 0x%" PRIx64 " val: 0x%…
47 stm32l4x5_gpio_update_idr(char *gpio, uint32_t old_idr, uint32_t new_idr) "GPIO%s from: 0x%x to: 0x…
48 stm32l4x5_gpio_pins(char *gpio, uint16_t disconnected, uint16_t high) "GPIO%s disconnected pins: 0x…
H A Dgpio_pwr.c2 * GPIO qemu power controller
8 * Virtual gpio driver which can be used on top of pl061
10 * case is gpio driver for secure world application (ARM
20 * two named input GPIO lines:
29 #define TYPE_GPIOPWR "gpio-pwr"
/qemu/include/hw/arm/
H A Darmsse.h62 * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
64 * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
71 * + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
72 * + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
73 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
74 * + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
75 * + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
78 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
79 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
80 * + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
[all …]
/qemu/include/standard-headers/linux/
H A Dvirtio_gpio.h8 /* Virtio GPIO Feature bits */
11 /* Virtio GPIO request types */
28 /* Virtio GPIO IRQ types */
42 /* Virtio GPIO Request / Response */
45 uint16_t gpio; member
59 /* Virtio GPIO IRQ Request / Response */
61 uint16_t gpio; member
/qemu/include/hw/input/
H A Di8042.h45 * + Named GPIO input "ps2-kbd-input-irq": set to 1 if the downstream PS2
47 * + Named GPIO input "ps2-mouse-input-irq": set to 1 if the downstream PS2
49 * + Named GPIO output "a20": A20 line for x86 PCs
50 * + Unnamed GPIO output 0-1: i8042 output irqs for keyboard (0) or mouse (1)
70 * + Named GPIO input "ps2-kbd-input-irq": set to 1 if the downstream PS2
72 * + Named GPIO input "ps2-mouse-input-irq": set to 1 if the downstream PS2
74 * + Unnamed GPIO output 0-1: i8042 output irqs for keyboard (0) or mouse (1)
/qemu/include/hw/gpio/
H A Dnrf51_gpio.h5 * + sysbus MMIO regions 0: GPIO registers
6 * + Unnamed GPIO inputs 0-31: Set tri-state input level for GPIO pin.
10 * + Unnamed GPIO outputs 0-31:
16 * + The nRF51 GPIO output driver supports two modes, standard and high-current
31 #define TYPE_NRF51_GPIO "nrf51_soc.gpio"
H A Dstm32l4x5_gpio.h2 * STM32L4x5 GPIO (General Purpose Input/Ouput)
25 #define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
36 /* GPIO registers */
48 /* GPIO registers reset values */
/qemu/hw/pci-host/
H A Darticia.c45 uint32_t gpio; /* bits 0-7 in, 8-15 out, 16-23 direction (0 in, 1 out) */ member
54 return (s->gpio >> (addr * 8)) & 0xff; in articia_gpio_read()
68 if ((s->gpio & (0xff << sh)) != (val & 0xff) << sh) { in articia_gpio_write()
69 s->gpio &= ~(0xff << sh | 0xff); in articia_gpio_write()
70 s->gpio |= (val & 0xff) << sh; in articia_gpio_write()
71 s->gpio |= bitbang_i2c_set(&s->smbus, BITBANG_I2C_SDA, in articia_gpio_write()
72 s->gpio & BIT(16) ? in articia_gpio_write()
73 !!(s->gpio & BIT(8)) : 1); in articia_gpio_write()
74 if ((s->gpio & BIT(17))) { in articia_gpio_write()
75 s->gpio &= ~BIT(0); in articia_gpio_write()
[all …]
/qemu/hw/core/
H A Dgpio.c2 * qdev GPIO helpers
56 name = "unnamed-gpio-in"; in qdev_init_gpio_in_named_with_opaque()
83 name = "unnamed-gpio-out"; in qdev_init_gpio_out_named()
121 name ? name : "unnamed-gpio-out", n); in qdev_connect_gpio_out_named()
125 "non-qdev-gpio[*]", OBJECT(input_pin)); in qdev_connect_gpio_out_named()
135 name ? name : "unnamed-gpio-out", n); in qdev_get_gpio_out_connector()
143 /* disconnect a GPIO output, returning the disconnected input (if any) */
149 name ? name : "unnamed-gpio-out", n); in qdev_disconnect_gpio_out_named()
180 const char *nm = ngl->name ? ngl->name : "unnamed-gpio-in"; in qdev_pass_gpios()
188 const char *nm = ngl->name ? ngl->name : "unnamed-gpio-out"; in qdev_pass_gpios()
/qemu/hw/arm/
H A Dbcm2838_peripherals.c38 /* GPIO */ in bcm2838_peripherals_init()
39 object_initialize_child(obj, "gpio", &s->gpio, TYPE_BCM2838_GPIO); in bcm2838_peripherals_init()
41 object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci", in bcm2838_peripherals_init()
43 object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost", in bcm2838_peripherals_init()
185 /* GPIO */ in bcm2838_peripherals_realize()
186 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { in bcm2838_peripherals_realize()
191 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0)); in bcm2838_peripherals_realize()
193 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->gpio), "sd-bus"); in bcm2838_peripherals_realize()
H A Db-l475e-iot01a.c33 #include "hw/gpio/stm32l4x5_gpio.h"
78 unsigned gpio, pin; in bl475e_init() local
95 object_initialize_child(OBJECT(machine), "gpio-out-splitters[*]", in bl475e_init()
105 gpio = dm163_input[i] / GPIO_NUM_PINS; in bl475e_init()
107 qdev_connect_gpio_out(DEVICE(&s->soc.gpio[gpio]), pin, in bl475e_init()
/qemu/hw/virtio/
H A Dvhost-user-gpio.c2 * Vhost-user GPIO virtio device
13 #include "hw/virtio/vhost-user-gpio.h"
26 /* Fixed for GPIO */ in vgpio_realize()
35 .name = "vhost-user-gpio",
/qemu/include/hw/core/
H A Dsplit-irq.h26 /* This is a simple device which has one GPIO input line and multiple
27 * GPIO output lines. Any change on the input line is forwarded to all
31 * + one unnamed GPIO input: the input line
32 * + N unnamed GPIO outputs: the output lines

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