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/linux/drivers/irqchip/
H A Dirq-gic.c5 * Interrupt architecture for the GIC:
42 #include <linux/irqchip/arm-gic.h>
50 #include "irq-gic-common.h"
114 * The GIC mapping of CPU interfaces does not necessarily match
116 * by the GIC itself.
309 pr_warn("GIC: PPI%ld is secure or misconfigured\n", gicirq - 16); in gic_set_type()
318 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ in gic_irq_set_vcpu_affinity()
337 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
338 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
353 * is read after we've read the ACK register on the GIC in gic_handle_irq()
400 struct gic_chip_data *gic = irq_data_get_irq_chip_data(d); gic_irq_print_chip() local
415 gic_get_cpumask(struct gic_chip_data * gic) gic_get_cpumask() argument
440 gic_cpu_if_up(struct gic_chip_data * gic) gic_cpu_if_up() argument
464 gic_dist_init(struct gic_chip_data * gic) gic_dist_init() argument
487 gic_cpu_init(struct gic_chip_data * gic) gic_cpu_init() argument
550 gic_dist_save(struct gic_chip_data * gic) gic_dist_save() argument
589 gic_dist_restore(struct gic_chip_data * gic) gic_dist_restore() argument
635 gic_cpu_save(struct gic_chip_data * gic) gic_cpu_save() argument
665 gic_cpu_restore(struct gic_chip_data * gic) gic_cpu_restore() argument
737 gic_pm_init(struct gic_chip_data * gic) gic_pm_init() argument
767 gic_pm_init(struct gic_chip_data * gic) gic_pm_init() argument
797 struct gic_chip_data *gic = irq_data_get_irq_chip_data(d); gic_set_affinity() local
1055 struct gic_chip_data *gic = d->host_data; gic_irq_domain_map() local
1163 gic_init_bases(struct gic_chip_data * gic,struct fwnode_handle * handle) gic_init_bases() argument
1238 __gic_init_bases(struct gic_chip_data * gic,struct fwnode_handle * handle) __gic_init_bases() argument
1267 gic_teardown(struct gic_chip_data * gic) gic_teardown() argument
1389 gic_of_setup(struct gic_chip_data * gic,struct device_node * node) gic_of_setup() argument
1415 gic_of_init_child(struct device * dev,struct gic_chip_data ** gic,int irq) gic_of_init_child() argument
1469 struct gic_chip_data *gic; gic_of_init() local
1638 struct gic_chip_data *gic = &gic_data[0]; gic_v2_acpi_init() local
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H A Dirq-gic-pm.c9 #include <linux/irqchip/arm-gic.h>
28 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_resume() local
39 * want to restore the GIC on the very first resume. So if in gic_runtime_resume()
42 if (!gic) in gic_runtime_resume()
45 gic_dist_restore(gic); in gic_runtime_resume()
46 gic_cpu_restore(gic); in gic_runtime_resume()
54 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_suspend() local
57 gic_dist_save(gic); in gic_runtime_suspend()
58 gic_cpu_save(gic); in gic_runtime_suspend()
115 dev_info(dev, "GIC IR in gic_probe()
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H A DMakefile30 obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
31 obj-$(CONFIG_ARM_GIC_PM) += irq-gic-pm.o
32 obj-$(CONFIG_ARCH_REALVIEW) += irq-gic-realview.o
34 obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o
35 obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-common.o
36 obj-$(CONFIG_ARM_GIC_ITS_PARENT) += irq-gic-its-msi-parent.o
37 obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v4.o
38 obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) += irq-gic-v3-its-fsl-mc-msi.o
40 obj-$(CONFIG_ARM_GIC_V5) += irq-gic-v5.o irq-gic-v5-irs.o irq-gic-v5-its.o \
41 irq-gic-v5-iwb.o
[all …]
H A Dirq-gic-realview.c3 * Special GIC quirks for the ARM RealView
11 #include <linux/irqchip/arm-gic.h>
58 /* The PB11MPCore GIC needs to be configured in the syscon */ in realview_gic_of_init()
69 pr_info("RealView GIC: set up interrupt controller to NEW mode, no DCC\n"); in realview_gic_of_init()
71 pr_err("RealView GIC setup: could not find syscon\n"); in realview_gic_of_init()
76 IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init);
77 IRQCHIP_DECLARE(armeb11mp_gic, "arm,eb11mp-gic", realview_gic_of_init);
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic
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H A Dmti,gic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
16 interrupts which can be used as IPIs. The GIC also includes a free-running
21 const: mti,gic
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
34 Base address and length of the GIC registers space. If not present,
42 Specifies the list of CPU interrupt vectors to which the GIC may not
55 Specifies the range of GIC interrupts that are reserved for IPIs.
69 MIPS GIC include
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H A Drenesas,rza1-irqc.yaml14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
43 description: Specifies the mapping from external interrupts to GIC interrupts.
63 #include <dt-bindings/interrupt-controller/arm-gic.h>
71 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
72 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
73 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
74 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
75 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
76 <5 0 &gic GIC_SP
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H A Darm,gic-v3.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
26 - qcom,msm8996-gic-v3
27 - const: arm,gic-v3
28 - const: arm,gic-v3
73 Specifies base physical address(s) and size of the GIC
75 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH)
79 - GIC Virtua
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H A Dfsl,ls-extirq.yaml49 description: Specifies the mapping from external interrupts to GIC interrupts.
105 # in parent interrupt controller, such as GIC.
122 #include <dt-bindings/interrupt-controller/arm-gic.h>
130 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
131 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
132 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
133 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
134 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
135 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-ns.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
75 gic: interrupt-controller@21000 { label
76 compatible = "arm,cortex-a9-gic";
106 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
109 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
110 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
111 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
112 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
113 <0x00007000 4 &gic GIC_SP
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H A Dbcm53573.dtsi9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
41 gic: interrupt-controller@1000 { label
42 compatible = "arm,cortex-a7-gic";
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <0x00002000 3 &gic GIC_SP
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/linux/arch/arm64/boot/dts/arm/
H A Dfvp-base-revc.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
222 gic: interrupt-controller@2f000000 { label
223 compatible = "arm,gic-v3";
238 compatible = "arm,gic-v3-its";
338 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
339 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
340 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
341 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
375 interrupt-map = <0 0 0 &gic
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/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2m.dtsi20 #include <dt-bindings/interrupt-controller/arm-gic.h>
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
39 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
40 <0 8 &gic GIC_SP
[all...]
H A Dvexpress-v2m-rs1.dtsi20 #include <dt-bindings/interrupt-controller/arm-gic.h>
111 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
112 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
113 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
114 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
115 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
116 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
117 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
118 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
119 <0 8 &gic GIC_SP
[all...]
/linux/arch/mips/include/asm/
H A Dmips-gic.h8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
16 /* The base address of the GIC registers */
19 /* Offsets from the GIC base address to various control blocks */
31 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
32 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
36 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
37 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
41 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
42 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
46 CPS_ACCESSOR_RW(gic, s
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/linux/Documentation/devicetree/bindings/bus/
H A Dbrcm,bus-axi.txt34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
43 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
44 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
45 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
/linux/arch/arm64/boot/dts/cavium/
H A Dthunder2-99xx.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
58 gic: interrupt-controller@4000080000 { label
59 compatible = "arm,gic-v3";
71 compatible = "arm,gic-v3-its";
73 reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
120 <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
121 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
122 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
123 0 0 0 4 &gic
[all...]
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi17 #include <dt-bindings/interrupt-controller/arm-gic.h>
147 interrupt-parent = <&gic>;
178 interrupt-parent = <&gic>;
209 interrupt-parent = <&gic>;
311 interrupt-parent = <&gic>;
508 interrupt-parent = <&gic>;
521 interrupt-parent = <&gic>;
539 interrupt-parent = <&gic>;
581 interrupt-parent = <&gic>;
594 interrupt-parent = <&gic>;
681 gic: interrupt-controller@f9010000 { global() label
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/linux/arch/arm/mach-ux500/
H A Dpm.c11 #include <linux/irqchip/arm-gic.h>
44 /* This function decouple the gic from the prcmu */
56 /* Wait a few cycles for the gic mask completion */ in prcmu_gic_decouple()
62 /* This function recouple the gic with the prcmu */
76 * This function checks if there are pending irq on the gic. It only
77 * makes sense if the gic has been decoupled before with the
126 * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
137 * This function copies the gic SPI settings to the prcmu in order to
185 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); in ux500_pm_init()
189 pr_err("could not remap GIC dis in ux500_pm_init()
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/linux/arch/mips/boot/dts/mti/
H A Dsead3.dts8 #include <dt-bindings/interrupt-controller/mips-gic.h>
43 gic: interrupt-controller@1b1c0000 { label
44 compatible = "mti,gic";
51 * Declare the interrupt-parent even though the mti,gic
63 interrupt-parent = <&gic>;
64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
226 interrupt-parent = <&gic>;
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
241 interrupt-parent = <&gic>;
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC
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/linux/arch/mips/boot/dts/mobileye/
H A Deyeq5.dtsi6 #include <dt-bindings/interrupt-controller/mips-gic.h>
116 interrupt-parent = <&gic>;
131 interrupt-parent = <&gic>;
146 interrupt-parent = <&gic>;
161 interrupt-parent = <&gic>;
176 interrupt-parent = <&gic>;
192 interrupt-parent = <&gic>;
205 interrupt-parent = <&gic>;
218 interrupt-parent = <&gic>;
236 gic label
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/linux/arch/arm64/boot/dts/apm/
H A Dapm-shadowcat.dtsi10 interrupt-parent = <&gic>;
120 gic: interrupt-controller@78090000 { label
121 compatible = "arm,cortex-a15-gic";
126 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
128 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
129 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
130 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
131 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
133 compatible = "arm,gic-v2m-frame";
138 compatible = "arm,gic
[all...]
/linux/arch/mips/boot/dts/ralink/
H A Dmt7621.dtsi2 #include <dt-bindings/interrupt-controller/mips-gic.h>
186 interrupt-parent = <&gic>;
223 interrupt-parent = <&gic>;
241 interrupt-parent = <&gic>;
261 interrupt-parent = <&gic>;
307 interrupt-parent = <&gic>;
334 interrupt-parent = <&gic>;
338 gic: interrupt-controller@1fbc0000 { label
339 compatible = "mti,gic";
348 compatible = "mti,gic
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/linux/tools/testing/selftests/kvm/arm64/
H A Dvgic_init.c168 TEST_ASSERT(ret && errno == EINVAL, "GIC dist base not aligned"); in subtest_dist_rdist()
173 TEST_ASSERT(ret && errno == EINVAL, "GIC redist/cpu base not aligned"); in subtest_dist_rdist()
201 TEST_ASSERT(ret && errno == EEXIST, "GIC redist base set again"); in subtest_dist_rdist()
479 "read GICR_TYPER before GIC initialized"); in test_v3_typer_accesses()
718 * Returns 0 if it's possible to create GIC device of a given type (V2 or V3).
740 TEST_ASSERT(ret < 0 && errno == EEXIST, "create GIC device twice"); in test_kvm_device()
749 "create GIC device while other version exists"); in test_kvm_device()
824 static void test_sysreg_array(int gic, const struct sr_def *sr, int nr, in test_sysreg_array() argument
844 ret = __kvm_has_device_attr(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, in test_sysreg_array()
849 ret = __kvm_device_attr_get(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREG in test_sysreg_array()
858 get_ctlr_pribits(int gic) get_ctlr_pribits() argument
874 check_unaccessible_el1_regs(int gic,const struct sr_def * sr,const char * what) check_unaccessible_el1_regs() argument
897 get_vtr_pribits(int gic) get_vtr_pribits() argument
913 check_unaccessible_el2_regs(int gic,const struct sr_def * sr,const char * what) check_unaccessible_el2_regs() argument
942 int gic; test_v3_sysregs() local
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/linux/drivers/net/ethernet/microsoft/mana/
H A Dgdma_main.c630 struct gdma_irq_context *gic; in mana_gd_register_irq() local
650 gic = xa_load(&gc->irq_contexts, msi_index); in mana_gd_register_irq()
651 if (WARN_ON(!gic)) in mana_gd_register_irq()
654 spin_lock_irqsave(&gic->lock, flags); in mana_gd_register_irq()
655 list_add_rcu(&queue->entry, &gic->eq_list); in mana_gd_register_irq()
656 spin_unlock_irqrestore(&gic->lock, flags); in mana_gd_register_irq()
664 struct gdma_irq_context *gic; in mana_gd_deregister_irq() local
677 gic = xa_load(&gc->irq_contexts, msix_index); in mana_gd_deregister_irq()
678 if (WARN_ON(!gic)) in mana_gd_deregister_irq()
681 spin_lock_irqsave(&gic in mana_gd_deregister_irq()
1431 struct gdma_irq_context *gic = arg; mana_gd_intr() local
1544 struct gdma_irq_context *gic; mana_gd_setup_dyn_irqs() local
1625 struct gdma_irq_context *gic; mana_gd_setup_irqs() local
1779 struct gdma_irq_context *gic; mana_gd_remove_irqs() local
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12345678910>>...65