| /qemu/docs/system/ppc/ |
| H A D | amigang.rst | 13 which is a rebranded Mai Logic Teron board with modified U-Boot
14 firmware to support AmigaOS 4.
17 ----------------
19 * PowerPC 7457 CPU (can also use ``-cpu g3, 750cxe, 750fx`` or ``750gx``)
24 * 4 KiB NVRAM (use ``-drive if=mtd,format=raw,file=nvram.bin`` to keep contents persistent)
26 Firmware section in Eyetech AmigaOne/Mai Logic Teron (``amigaone``)
27 --------
29 A firmware binary is necessary for the boot process. It is a modified
30 U-Boot under GPL but its source is lost so it cannot be included in
32 https://www.hyperion-entertainment.com/index.php/downloads?view=files&parent=28.
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| H A D | powermac.rst | 4 Use the executable ``qemu-system-ppc`` to simulate a complete PowerMac
7 - ``g3beige`` Heathrow based PowerMac
8 - ``mac99`` Mac99 based PowerMac
11 -----------------
17 * 2 PMAC IDE interfaces with hard disk and CD-ROM support
20 * VIA-CUDA with ADB keyboard and mouse.
24 ---------------
28 Firmware chapter
29 --------
33 (GPL v2) portable firmware implementation. The goal is to implement a
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| H A D | ppce500.rst | 8 -----------------
19 * Power-off functionality via one GPIO pin
26 ----------------------------------
29 which it passes to the guest, if there is no ``-dtb`` option. This provides
33 If users want to provide their own DTB, they can use the ``-dtb`` option.
36 * The number of subnodes under /cpus node should match QEMU's ``-smp`` option
37 * The /memory reg size should match QEMU’s selected ram_size via ``-m``
39 Both ``qemu-system-ppc`` and ``qemu-system-ppc64`` provide emulation for the
40 following 32-bit PowerPC CPUs:
45 Additionally ``qemu-system-ppc64`` provides support for the following 64-bit
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| /qemu/tests/qtest/ |
| H A D | prom-env-test.c | 2 * Test Open-Firmware-based machines.
10 * or later. See the COPYING file in the top-level directory.
12 * This test is used to check that some Open Firmware based machines (i.e.
14 * first put some Forth code into the "boot-command" Open Firmware environment
15 * variable. This Forth code writes a well-known magic value to a known location
16 * in memory. Then we start the guest so that the firmware can boot and finally
24 #include "ppc-util.h"
52 * The pseries firmware boots much faster without the default in test_machine()
57 extra_args = "-nodefaults" in test_machine()
58 " -machine " PSERIES_DEFAULT_CAPABILITIES; in test_machine()
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| /qemu/docs/system/arm/ |
| H A D | stm32.rst | 1 STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vl…
4 The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
7 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
9 The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
10 based on this chip :
12 - ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
14 The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
15 based on this chip :
17 - ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller
19 The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L4
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| H A D | b-l475e-iot01a.rst | 1 B-L475E-IOT01A IoT Node (``b-l475e-iot01a``)
4 The B-L475E-IOT01A IoT Node uses the STM32L475VG SoC which is based on
5 ARM Cortex-M4F core. It is part of STMicroelectronics
7 ultra-low power series. The STM32L4x5 chip runs at up to 80 MHz and
8 integrates 128 KiB of SRAM and up to 1MiB of Flash. The B-L475E-IOT01A board
15 Currently B-L475E-IOT01A machines support the following devices:
17 - Cortex-M4F based STM32L4x5 SoC
18 - STM32L4x5 EXTI (Extended interrupts and events controller)
19 - STM32L4x5 SYSCFG (System configuration controller)
20 - STM32L4x5 RCC (Reset and clock control)
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| H A D | nuvoton.rst | 1 Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj`…
4 The `Nuvoton iBMC`_ chips are a family of Arm-based SoCs that are
7 NPCM8XX series. NPCM7XX series feature one or two Arm Cortex-A9 CPU cores,
8 while NPCM8XX feature 4 Arm Cortex-A35 CPU cores. Both series contain a
12 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
14 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise
15 segment. The following machines are based on this chip :
17 - ``npcm750-evb`` Nuvoton NPCM750 Evaluation board
19 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
20 Hyperscale applications. The following machines are based on this chip :
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| H A D | nrf.rst | 4 The `Nordic nRF`_ chips are a family of ARM-based System-on-Chip that
5 are designed to be used for low-power and short-range wireless solutions.
11 The following machines are based on this chip :
13 - ``microbit`` BBC micro:bit board with nRF51822 SoC
19 -----------------
21 * ARM Cortex-M0 (ARMv6-M)
31 ---------------
34 * Real-Time Clock (RTC) controller
42 ------------
44 The Micro:bit machine can be started using the ``-device`` option to load a
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| H A D | aspeed.rst | 1 …-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280…
5 Aspeed evaluation boards. They are based on different releases of the
6 Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
8 with dual cores ARM Cortex-A7 CPUs (1.2GHz).
13 AST2400 SoC based machines :
15 - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
16 - ``quanta-q71l-bmc`` OpenBMC Quanta BMC
17 - ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
18 - ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
20 AST2500 SoC based machines :
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| H A D | digic.rst | 1 Canon A1100 (``canon-a1100``)
5 uses the DIGIC SoC. This model is based on reverse engineering efforts
10 to run the original camera firmware, but it can successfully run
|
| H A D | raspi.rst | 8 ARM1176JZF-S core, 512 MiB of RAM
10 Cortex-A7 (4 cores), 1 GiB of RAM
12 Cortex-A53 (4 cores), 512 MiB of RAM
14 Cortex-A53 (4 cores), 1 GiB of RAM
16 Cortex-A72 (4 cores), 2 GiB of RAM
19 -------------------
21 * ARM1176JZF-S, Cortex-A7, Cortex-A53 or Cortex-A72 CPU
27 * Serial ports (BCM2835 AUX - 16550 based - and PL011)
36 * VideoCore firmware (property)
41 ---------------
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| H A D | xlnx-versal-virt.rst | 1 Xilinx Versal Virt (``xlnx-versal-virt``)
4 Xilinx Versal is a family of heterogeneous multi-core SoCs
10 https://www.xilinx.com/products/silicon-devices/acap/versal.html
22 - 2 ACPUs (ARM Cortex-A72)
26 - Interrupt controller (ARM GICv3)
27 - 2 UARTs (ARM PL011)
28 - An RTC (Versal built-in)
29 - 2 GEMs (Cadence MACB Ethernet MACs)
30 - 8 ADMA (Xilinx zDMA) channels
31 - 2 SD Controllers
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| /qemu/include/hw/riscv/ |
| H A D | boot_opensbi.h | 1 /* SPDX-License-Identifier: BSD-2-Clause */
5 * Based on include/sbi/{fw_dynamic.h,sbi_scratch.h} from the OpenSBI project.
11 #include "exec/cpu-defs.h"
47 * address as the FW_DYNAMIC firmware. In this case, the relocation
50 * stage leading to boot-time crash. To avoid this boot-time crash,
52 * to the FW_DYNAMIC firmware as the preferred boot HART.
55 * stage can set it to -1UL which will force the FW_DYNAMIC firmware
77 * address as the FW_DYNAMIC firmware. In this case, the relocation
80 * stage leading to boot-time crash. To avoid this boot-time crash,
82 * to the FW_DYNAMIC firmware as the preferred boot HART.
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| /qemu/docs/specs/ |
| H A D | ppc-spapr-hcalls.rst | 5 When used with the ``pseries`` machine type, ``qemu-system-ppc64`` implements
11 The subset in LoPAR is selected based on the requirements of Linux as a guest.
14 calls which are mostly used as a private interface between the firmware
23 RTAS stands for Run-Time Abstraction Sercies and is a set of runtime services
24 generally provided by the firmware inside the guest to the operating system. It
26 Firmware) and is still used by PAPR and LoPAR to provide various services that
30 "firmware" blob in the guest is a small stub of a few instructions which
54 non-cacheable accesses to any guest physical addresses that the
57 This is typically used by the firmware running in the guest.
66 is used by our SLOF firmware to invert the screen.
|
| H A D | acpi_nvdimm.rst | 1 QEMU<->ACPI BIOS NVDIMM interface
8 ----------------------
12 to be supported by platform, platform firmware also exposes an ACPI
67 _FIT(Firmware Interface Table)
77 NVDIMM Firmware Interface Table (NFIT).
80 --------------------------
82 QEMU uses 4 bytes IO Port starting from 0x0a18 and a RAM-based memory page
90 This page is RAM-based and it is used to transfer data between _DSM
95 ACPI writes _DSM Input Data (based on the offset in the page):
97 [0x0 - 0x3]
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| H A D | acpi_cpu_hotplug.rst | 1 QEMU<->ACPI BIOS CPU hotplug interface
7 ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
8 and hot-remove events.
12 -------------------------------------------
16 - ICH9-LPC (IO port 0x0cd8-0xcf7, 1-byte access)
17 - PIIX-PM (IO port 0xaf00-0xaf1f, 1-byte access)
18 - One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
19 - The first DWORD in bitmap is used in write mode to switch from legacy
22 QEMU sets corresponding CPU bit on hot-add event and issues SCI
24 to notify OS about CPU hot-add events. CPU hot-remove isn't supported.
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| /qemu/docs/system/i386/ |
| H A D | tdx.rst | 5 Virtual Machine Extensions (VMX) and Multi-Key Total Memory Encryption (MKTME)
12 -------------
18 Trust Domain Virtual Firmware (TDVF)
21 Trust Domain Virtual Firmware (TDVF) is required to provide TD services to boot
29 device and it actually works as RAM. "-bios" option is chosen to load TDVF.
31 OVMF is the opensource firmware that implements the TDVF support. Thus the
32 command line to specify and load TDVF is ``-bios OVMF.fd``
35 ---------------------
37 Unlike non-TDX VM, the CPU features (enumerated by CPU or MSR) of a TD are not
43 - Attributes:
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| H A D | sgx.rst | 5 --------
16 -----------
36 require -maxmem as EPC is not treated as {cold,hot}plugged memory.
43 The following QEMU snippet creates two EPC sections, with 64M pre-allocated
46 -object memory-backend-epc,id=mem1,size=64M,prealloc=on \
47 -object memory-backend-epc,id=mem2,size=28M \
48 -M sgx-epc.0.memdev=mem1,sgx-epc.1.memdev=mem2
79 in any of QEMU's built-in CPU configuration. To expose SGX (and SGX Launch
80 Control) to a guest, you must either use ``-cpu host`` to pass-through the
81 host CPU model, or explicitly enable SGX when using a built-in CPU model,
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| /qemu/hw/arm/ |
| H A D | xlnx-zcu102.c | 20 #include "hw/arm/xlnx-zynqmp.h"
23 #include "qemu/error-report.h"
43 #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
51 return s->secure; in OBJECT_DECLARE_SIMPLE_TYPE()
58 s->secure = value; in zcu102_set_secure()
65 return s->virt; in zcu102_get_virt()
72 s->virt = value; in zcu102_set_virt()
84 /* If EL3 is enabled, we keep all firmware nodes active. */ in zcu102_modify_dtb()
85 if (!s->secure) { in zcu102_modify_dtb()
86 node_path = qemu_fdt_node_path(fdt, NULL, "xlnx,zynqmp-firmware", in zcu102_modify_dtb()
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| H A D | digic_boards.c | 6 * This model is based on reverse engineering efforts
30 #include "qemu/error-report.h"
55 if (machine->ram_size != mc->default_ram_size) { in digic4_board_init()
56 char *sz = size_to_str(mc->default_ram_size); in digic4_board_init()
67 memory_region_add_subregion(get_system_memory(), 0, machine->ram); in digic4_board_init()
69 if (board->add_rom0) { in digic4_board_init()
70 board->add_rom0(s, DIGIC4_ROM0_BASE, in digic4_board_init()
71 machine->firmware ?: board->rom0_def_filename); in digic4_board_init()
74 if (board->add_rom1) { in digic4_board_init()
75 board->add_rom1(s, DIGIC4_ROM1_BASE, in digic4_board_init()
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| /qemu/include/hw/arm/ |
| H A D | raspberrypi-fw-defs.h | 2 * Raspberry Pi firmware definitions
4 * Copyright (C) 2022 Auriga LLC, based on Linux kernel
5 * `include/soc/bcm2835/raspberrypi-firmware.h` (Copyright © 2015 Broadcom)
7 * SPDX-License-Identifier: GPL-2.0-or-later
|
| /qemu/.gitlab-ci.d/opensbi/ |
| H A D | Dockerfile | 2 # Docker image to cross-compile OpenSBI firmware binaries
13 apt install --assume-yes --no-install-recommends \
14 build-essential \
15 ca-certificates \
22 rm -rf /var/lib/apt/lists/*
24 # Manually install the kernel.org "Crosstool" based toolchains for gcc-8.3
25 RUN wget -O - \
26 …ge.kernel.org/pub/tools/crosstool/files/bin/x86_64/8.3.0/x86_64-gcc-8.3.0-nolibc-riscv32-linux.tar…
27 | tar -C /opt -xJ
28 RUN wget -O - \
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| /qemu/docs/system/riscv/ |
| H A D | shakti-c.rst | 4 Shakti C Reference Platform is a reference platform based on arty a7 100t
7 Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C
11 https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/fpga/boards/artya7-100t/c-class/REA…
13 For more info on the Shakti C-class core, please see:
14 https://c-class.readthedocs.io/en/latest/
17 -----------------
21 * 1 C-class core
23 * Platform-Level Interrupt Controller (PLIC)
27 ------------
29 The ``shakti_c`` machine can start using the standard -bios
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| /qemu/docs/ |
| H A D | igd-assign.txt | 1 Intel Graphics Device (IGD) assignment with vfio-pci
4 Using vfio-pci, we can passthrough Intel Graphics Device (IGD) to guest, either
16 (*-Required by)
19 |---------------------------------------------|-------|---------|-------|---------|
30 For #1, the "x-igd-opregion=on" option exposes a copy of host IGD OpRegion to
31 guest via fw_cfg, where guest firmware can set up guest OpRegion with it.
33 For #2, "x-igd-lpc=on" option copies the IDs of host LPC bridge and host bridge
42 For #5, "x-vga=on" enables guest access to standard VGA IO/MMIO ranges.
46 "Guest firmware" section.
57 x-igd-opregion=on,x-igd-lpc=on,x-vga=on
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| /qemu/docs/devel/testing/ |
| H A D | functional.rst | 1 .. _checkfunctional-ref:
17 Note that if you don't use one of the QemuBaseTest based classes for your
19 that there is no TAP-incompatible output written to stdio, e.g. either by
24 Tests based on ``qemu_test.QemuSystemTest`` can easily:
36 * Download (and cache) remote data files, such as firmware and kernel
40 -------------
46 make check-functional
53 make check-functional-x86_64
63 $ export QEMU_TEST_QEMU_BINARY=$PWD/qemu-system-x86_64
73 -------
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