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/linux-6.8/Documentation/devicetree/bindings/net/can/
Dxilinx,can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
31 clock-names:
34 power-domains:
[all …]
/linux-6.8/Documentation/devicetree/bindings/net/
Daltr,tse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Chevallier <maxime.chevallier@bootlin.com>
15 - const: altr,tse-1.0
16 - const: ALTR,tse-1.0
18 - const: altr,tse-msgdma-1.0
23 interrupt-names:
25 - const: rx_irq
26 - const: tx_irq
[all …]
Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
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Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
33 adi,fifo-depth-bits:
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Dqcom,ethqos.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
17 - $ref: snps,dwmac.yaml#
22 - qcom,qcs404-ethqos
23 - qcom,sa8775p-ethqos
24 - qcom,sc8280xp-ethqos
25 - qcom,sm8150-ethqos
30 reg-names:
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/linux-6.8/drivers/staging/axis-fifo/
Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
19 - interrupt-parent: Should be <&intc>
[all …]
Daxis-fifo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
12 /* ----------------------------
14 * ----------------------------
37 /* ----------------------------
39 * ----------------------------
47 /* ----------------------------
49 * ----------------------------
68 /* ----------------------------
70 * ----------------------------
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/linux-6.8/sound/soc/meson/
Daxg-fifo.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
14 #include <sound/soc-dai.h>
16 #include "axg-fifo.h"
20 * capture frontend DAI. The logic behind this two types of fifo is very
48 struct snd_soc_pcm_runtime *rtd = ss->private_data; in axg_fifo_dai()
64 return dai->dev; in axg_fifo_dev()
67 static void __dma_enable(struct axg_fifo *fifo, bool enable) in __dma_enable() argument
69 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN, in __dma_enable()
76 struct axg_fifo *fifo = axg_fifo_data(ss); in axg_fifo_pcm_trigger() local
82 __dma_enable(fifo, true); in axg_fifo_pcm_trigger()
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Daxg-frddr.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
16 #include <sound/soc-dai.h>
18 #include "axg-fifo.h"
37 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); in g12a_frddr_dai_prepare() local
40 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
42 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
44 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
54 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); in axg_frddr_dai_hw_params() local
55 unsigned int period, depth, val; in axg_frddr_dai_hw_params() local
59 /* Trim the FIFO depth if the period is small to improve latency */ in axg_frddr_dai_hw_params()
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/linux-6.8/Documentation/devicetree/bindings/spi/
Dcdns,qspi-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
14 - if:
18 const: xlnx,versal-ospi-1.0
21 - power-domains
22 - if:
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Dspi-sifive.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: spi-controller.yaml#
20 - enum:
21 - sifive,fu540-c000-spi
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/linux-6.8/include/linux/soc/qcom/
Dgeni-se.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
15 * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO
56 * struct geni_se - GENI Serial Engine
258 * For QUP HW Version >= 3.10 Tx fifo depth support is increased
269 * For QUP HW Version >= 3.10 Rx fifo depth support is increased
309 * geni_se_read_proto() - Read the protocol configured for a serial engine
318 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); in geni_se_read_proto()
324 * geni_se_setup_m_cmd() - Setup the primary sequencer
337 writel(m_cmd, se->base + SE_GENI_M_CMD0); in geni_se_setup_m_cmd()
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/linux-6.8/Documentation/devicetree/bindings/sound/
Damlogic,axg-fifo.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/amlogic,axg-fifo.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic AXG Audio FIFO controllers
10 - Jerome Brunet <jbrunet@baylibre.com>
15 - enum:
16 - amlogic,axg-toddr
17 - amlogic,axg-frddr
18 - items:
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Dfsl,esai.txt3 The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
10 - compatible : Compatible list, should contain one of the following
12 "fsl,imx35-esai",
13 "fsl,vf610-esai",
14 "fsl,imx6ull-esai",
15 "fsl,imx8qm-esai",
17 - reg : Offset and length of the register set for the device.
19 - interrupts : Contains the spdif interrupt.
21 - dmas : Generic dma devicetree binding as described in
24 - dma-names : Two dmas have to be defined, "tx" and "rx".
[all …]
/linux-6.8/Documentation/networking/device_drivers/can/freescale/
Dflexcan.rst1 .. SPDX-License-Identifier: GPL-2.0+
7 Authors: Marc Kleine-Budde <mkl@pengutronix.de>,
15 - FIFO
16 - mailbox
20 configured for RX-FIFO mode.
22 The RX FIFO mode uses a hardware FIFO with a depth of 6 CAN frames,
23 while the mailbox mode uses a software FIFO with a depth of up to 62
30 With the "rx-rtr" private flag the ability to receive RTR frames can
34 "rx-rtr" on
40 more performant "RX mailbox" mode and will use "RX FIFO" mode
[all …]
/linux-6.8/arch/arm64/boot/dts/amlogic/
Dmeson-sm1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-sm1-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
16 tdmif_a: audio-controller-0 {
17 compatible = "amlogic,axg-tdm-iface";
18 #sound-dai-cells = <0>;
19 sound-name-prefix = "TDM_A";
[all …]
Dmeson-g12.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-g12-common.dtsi"
8 #include <dt-bindings/clock/axg-audio-clkc.h>
9 #include <dt-bindings/power/meson-g12a-power.h>
10 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
11 #include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h>
14 tdmif_a: audio-controller-0 {
15 compatible = "amlogic,axg-tdm-iface";
16 #sound-dai-cells = <0>;
17 sound-name-prefix = "TDM_A";
[all …]
/linux-6.8/Documentation/devicetree/bindings/i2c/
Dcdns,i2c-r1p10.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - cdns,i2c-r1p10 # cadence i2c controller version 1.0
19 - cdns,i2c-r1p14 # cadence i2c controller version 1.4
33 clock-frequency:
39 clock-name:
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/linux-6.8/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/linux-6.8/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/linux-6.8/drivers/i2c/busses/
Di2c-xiic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
56 * struct xiic_i2c - Internal representation of the XIIC I2C bus
67 * @endianness: big/little-endian byte order
68 * @clk: Pointer to AXI4-lite input clock
106 * struct timing_regs - AXI I2C timing registers that depend on I2C spec
[all …]
/linux-6.8/drivers/spi/
Dspi-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
24 #define CDNS_SPI_NAME "cdns-spi"
37 #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
62 * SPI Configuration Register - Baud rate and target select
81 #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
83 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
101 * struct cdns_spi - This definition defines spi driver instance
113 * @tx_fifo_depth: Depth of the TX FIFO
[all …]
/linux-6.8/arch/arm64/boot/dts/ti/
Dk3-j721e-evm-gesi-exp-board.dtso1 // SPDX-License-Identifier: GPL-2.0
8 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/net/ti-dp83867.h>
17 #include "k3-pinctrl.h"
21 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
22 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
23 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
24 ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
[all …]
/linux-6.8/Documentation/devicetree/bindings/mmc/
Dsynopsys-dw-mshc-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: mmc-controller.yaml#
13 - Ulf Hansson <ulf.hansson@linaro.org>
20 reset-names:
23 clock-frequency:
29 fifo-depth:
31 The maximum size of the tx/rx fifo's. If this property is not
[all …]

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