1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
16 #include <sound/soc-dai.h>
18 #include "axg-fifo.h"
37 	struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);  in g12a_frddr_dai_prepare()  local
40 	regmap_update_bits(fifo->map, FIFO_CTRL1,  in g12a_frddr_dai_prepare()
42 	regmap_update_bits(fifo->map, FIFO_CTRL1,  in g12a_frddr_dai_prepare()
44 	regmap_update_bits(fifo->map, FIFO_CTRL1,  in g12a_frddr_dai_prepare()
54 	struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);  in axg_frddr_dai_hw_params()  local
55 	unsigned int period, depth, val;  in axg_frddr_dai_hw_params()  local
59 	/* Trim the FIFO depth if the period is small to improve latency */  in axg_frddr_dai_hw_params()
60 	depth = min(period, fifo->depth);  in axg_frddr_dai_hw_params()
61 	val = (depth / AXG_FIFO_BURST) - 1;  in axg_frddr_dai_hw_params()
62 	regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK,  in axg_frddr_dai_hw_params()
71 	struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);  in axg_frddr_dai_startup()  local
74 	/* Enable pclk to access registers and clock the fifo ip */  in axg_frddr_dai_startup()
75 	ret = clk_prepare_enable(fifo->pclk);  in axg_frddr_dai_startup()
80 	regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0);  in axg_frddr_dai_startup()
88 	struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);  in axg_frddr_dai_shutdown()  local
90 	clk_disable_unprepare(fifo->pclk);  in axg_frddr_dai_shutdown()
372 		.compatible = "amlogic,axg-frddr",
375 		.compatible = "amlogic,g12a-frddr",
378 		.compatible = "amlogic,sm1-frddr",
387 		.name = "axg-frddr",
393 MODULE_DESCRIPTION("Amlogic AXG/G12A playback fifo driver");