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/qemu/scripts/
H A Dmeson-buildoptions.sh38 printf "%s\n" ' (choices: auto/disabled/enabled/internal/system)'
92 printf "%s\n" 'Optional features, enabled with --enable-FEATURE and'
93 printf "%s\n" 'disabled with --disable-FEATURE, default is enabled if available'
234 --enable-af-xdp) printf "%s" -Daf_xdp=enabled ;;
236 --enable-alsa) printf "%s" -Dalsa=enabled ;;
240 --enable-attr) printf "%s" -Dattr=enabled ;;
243 --enable-auth-pam) printf "%s" -Dauth_pam=enabled ;;
250 --enable-blkio) printf "%s" -Dblkio=enabled ;;
256 --enable-bochs) printf "%s" -Dbochs=enabled ;;
258 --enable-bpf) printf "%s" -Dbpf=enabled ;;
[all …]
H A Dmodinfo-generate.py35 def generate(name, lines, enabled): argument
52 # don't add a module which dependency is not enabled
54 if data.strip() not in enabled:
55 print(" /* module {} isn't enabled in Kconfig. */"
88 # get all devices enabled in kconfig, from *-config-device.mak
89 enabled = set()
94 enabled.add(config[0][7:]) # remove CONFIG_
104 moddeps = generate(basename, lines, enabled)
H A Dmeson-buildoptions.py90 return "enabled" if value else "disabled"
126 # than "auto", "enabled", and "disabled".
132 return not (set(opt["choices"]) <= {"auto", "disabled", "enabled"})
137 # combos require an argument if they accept neither "enabled"
144 return not ({"enabled", "disabled"}.intersection(opt["choices"]))
200 if opt["type"] == "combo" and "enabled" in opt["choices"]:
209 sh_print("Optional features, enabled with --enable-FEATURE and")
210 sh_print("disabled with --disable-FEATURE, default is enabled if available")
234 if opt["type"] == "combo" and "enabled" in opt["choices"]:
235 print(f' --enable-{key}) printf "%s" -D{name}=enabled ;;')
/qemu/docs/system/arm/
H A Dcpu-features.rst6 corresponding boolean CPU proprieties that, when enabled, indicate
19 support the AArch32 CPU feature, which may be enabled by disabling the
56 enabled, as they are all ``true``. (The ``sve<N>`` CPU features are all
81 "'aarch64' feature cannot be disabled unless KVM is enabled and 32-bit EL1 is supported"
127 seattle host, but mostly if KVM is enabled the ``host`` CPU type must be
133 do if we want to launch guests without all the host's CPU features enabled.
138 When KVM is enabled, only the ``max``, ``host``, and current CPU type may be
142 above, the ``cortex-a57`` CPU type is also valid when KVM is enabled.
147 some time. Additionally, if the KVM-enabled QEMU instance running on a
155 given CPU type, then they may be selectively enabled or disabled on the
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/qemu/docs/system/i386/
H A Dhyperv.rst22 No Hyper-V enlightenments are enabled by default by either KVM or QEMU. In
23 QEMU, individual enlightenments can be enabled through CPU flags, e.g:
32 When any set of the Hyper-V enlightenments is enabled, QEMU changes hypervisor
80 page (enabled via MSR HV_X64_MSR_REFERENCE_TSC, 0x40000021). Both clocksources
87 When enabled, this enlightenment provides additional communication facilities
134 itself by writing to it. Even when this MSR is enabled, it is not a recommended
144 enabled, it provides HV_X64_MSR_REENLIGHTENMENT_CONTROL (0x40000106),
161 enabled, it provides Enlightened VMCS version 1 feature to the guest. The feature
166 hv-evmcs is enabled. It may make sense to measure your nested workload with and
176 enabled.
[all …]
H A Dkvm-pv.rst14 features are enabled by default for any CPU model when ``KVM`` acceleration is
15 enabled:
24 ``kvm-msi-ext-dest-id`` feature is enabled by default in x2apic mode with split
46 Note: since Linux v5.10 the feature is deprecated and not enabled by ``KVM``.
/qemu/hw/intc/
H A Dimx_avic.c43 VMSTATE_UINT64(enabled, IMXAVICState),
63 uint64_t new = s->pending & s->enabled; in imx_avic_update()
126 case 4: /* Interrupt Enabled Number Register High */ in imx_avic_read()
127 return s->enabled >> 32; in imx_avic_read()
129 case 5: /* Interrupt Enabled Number Register Low */ in imx_avic_read()
130 return s->enabled & 0xffffffffULL; in imx_avic_read()
156 uint64_t flags = s->pending & s->enabled & ~s->is_fiq; in imx_avic_read()
177 uint64_t flags = s->pending & s->enabled & s->is_fiq; in imx_avic_read()
196 return (s->pending & s->enabled & ~s->is_fiq) >> 32; in imx_avic_read()
199 return (s->pending & s->enabled & ~s->is_fiq) & 0xffffffffULL; in imx_avic_read()
[all …]
H A Dgoldfish_pic.c45 "goldfish-pic.%d: pending=0x%08x enabled=0x%08x\n", in goldfish_pic_print_info()
46 s->idx, s->pending, s->enabled); in goldfish_pic_print_info()
51 if (s->pending & s->enabled) { in goldfish_pic_update()
82 value = ctpop32(s->pending & s->enabled); in goldfish_pic_read()
86 value = s->pending & s->enabled; in goldfish_pic_read()
109 s->enabled = 0; in goldfish_pic_write()
113 s->enabled &= ~value; in goldfish_pic_write()
116 s->enabled |= value; in goldfish_pic_write()
143 s->enabled = 0; in goldfish_pic_reset()
166 VMSTATE_UINT32(enabled, GoldfishPICState),
H A Darm_gicv3_dist.c309 /* This GIC implementation always has affinity routing enabled, in gicd_readb()
329 /* This GIC implementation always has affinity routing enabled, in gicd_writeb()
388 * NS affinity routing is enabled, otherwise RES0 in gicd_readl()
390 * NS affinity routing is not enabled, otherwise RES0 in gicd_readl()
391 * Since for QEMU affinity routing is always enabled in gicd_readl()
410 * LPIS == 1 (LPIs are supported if affinity routing is enabled) in gicd_readl()
464 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, in gicd_readl()
468 *data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL, in gicd_readl()
500 /* RAZ/WI since affinity routing is always enabled */ in gicd_readl()
531 * security enabled and this is an NS access in gicd_readl()
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/qemu/hw/core/
H A Dptimer.c24 uint8_t enabled; /* 0 = disabled, 1 = periodic, 2 = oneshot. */ member
91 s->enabled = 0; in ptimer_reload()
102 if (s->enabled == 1 && s->limit == 0) { in ptimer_reload()
114 if (s->enabled == 1 && s->limit != 0) { in ptimer_reload()
120 if (s->enabled == 0) { in ptimer_reload()
128 s->enabled = 0; in ptimer_reload()
141 if (s->enabled == 1 && (delta * period < 10000) && in ptimer_reload()
169 if (s->enabled == 2) { in ptimer_tick()
171 s->enabled = 0; in ptimer_tick()
205 if (s->enabled && s->delta != 0) { in ptimer_get_count()
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/qemu/include/hw/s390x/
H A Dstorage-keys.h33 * Check whether storage keys are enabled. If not enabled, they were not
34 * enabled lazily either by the guest via a storage key instruction or
43 * Returns false if not enabled and true if enabled.
53 * if storage keys were not enabled before this call.
57 * Returns false if not enabled before this call, and true if already
58 * enabled.
66 * storage keys have not been lazily enabled yet.
83 * storage keys have not been lazily enabled yet and implicit
/qemu/hw/net/rocker/
H A Drocker_fp.c35 bool enabled; member
59 value->enabled = port->enabled; in fp_port_get_info()
124 if (port->enabled) { in fp_port_eg()
139 * transitions to enabled. in fp_port_receive_iov()
142 if (!port->enabled) { in fp_port_receive_iov()
198 return port->enabled; in fp_port_enabled()
214 port->enabled = true; in fp_port_enable()
215 DPRINTF("port %d enabled\n", port->index); in fp_port_enable()
220 port->enabled = false; in fp_port_disable()
/qemu/
H A D.patchew.yml25 enabled: true
42 enabled: true
65 enabled: true
121 enabled: true
128 enabled: false
135 enabled: true
143 enabled: true
150 enabled: false
179 enabled: false
208 enabled: true
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H A Dcpu-target.c37 void cpu_single_step(CPUState *cpu, int enabled) in cpu_single_step() argument
39 if (cpu->singlestep_enabled != enabled) { in cpu_single_step()
40 cpu->singlestep_enabled = enabled; in cpu_single_step()
49 trace_breakpoint_singlestep(cpu->cpu_index, enabled); in cpu_single_step()
/qemu/scripts/tracetool/format/
H A Dh.py39 enabled = 0
41 enabled = 1
44 out('#define TRACE_%(name)s_ENABLED %(enabled)d',
46 enabled=enabled)
47 out('#define TRACE_%s_ENABLED %d' % (e.name.upper(), enabled))
/qemu/hw/watchdog/
H A Dwdt_diag288.c28 VMSTATE_BOOL(enabled, DIAG288State),
37 diag288->enabled = false; in wdt_diag288_reset()
71 diag288->enabled = true; in wdt_diag288_handle_timer()
74 if (!diag288->enabled) { in wdt_diag288_handle_timer()
82 if (!diag288->enabled) { in wdt_diag288_handle_timer()
85 diag288->enabled = false; in wdt_diag288_handle_timer()
H A Dwdt_i6300esb.c86 int locked; /* If true, enabled field cannot be changed. */
87 int enabled; /* If true, watchdog is enabled. */ member
109 /* This function is called when the watchdog has either been enabled in OBJECT_DECLARE_SIMPLE_TYPE()
116 if (!d->enabled) in OBJECT_DECLARE_SIMPLE_TYPE()
164 d->enabled = 0; in i6300esb_reset()
228 old = d->enabled; in i6300esb_config_write()
229 d->enabled = (data & ESB_WDT_ENABLE) != 0; in i6300esb_config_write()
230 if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */ in i6300esb_config_write()
232 else if (!d->enabled) in i6300esb_config_write()
257 (d->enabled ? ESB_WDT_ENABLE : 0); in i6300esb_config_read()
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/qemu/tests/functional/
H A Dtest_mem_addr_space.py66 self.vm.set_qmp_monitor(enabled=False)
84 self.vm.set_qmp_monitor(enabled=False)
101 self.vm.set_qmp_monitor(enabled=False)
119 self.vm.set_qmp_monitor(enabled=False)
136 self.vm.set_qmp_monitor(enabled=False)
156 self.vm.set_qmp_monitor(enabled=False)
184 self.vm.set_qmp_monitor(enabled=False)
205 self.vm.set_qmp_monitor(enabled=False)
222 self.vm.set_qmp_monitor(enabled=False)
239 self.vm.set_qmp_monitor(enabled=False)
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/qemu/qapi/
H A Dqmp-registry.c29 cmd->enabled = true; in qmp_register_command()
48 bool enabled, const char *disable_reason) in qmp_toggle_command() argument
54 cmd->enabled = enabled; in qmp_toggle_command()
74 return cmd->enabled; in qmp_command_is_enabled()
/qemu/hw/timer/
H A Dsh_timer.c46 int enabled; member
104 if (s->enabled) { in sh_timer_write()
186 if (s->enabled) { in sh_timer_write()
187 /* Restart the timer if still enabled. */ in sh_timer_write()
209 trace_sh_timer_start_stop(enable, s->enabled); in sh_timer_start_stop()
211 if (s->enabled && !enable) { in sh_timer_start_stop()
214 if (!s->enabled && enable) { in sh_timer_start_stop()
218 s->enabled = !!enable; in sh_timer_start_stop()
224 s->int_level = s->enabled; in sh_timer_tick()
239 s->enabled = 0; in sh_timer_init()
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c74 bool enabled) in riscv_cpu_write_misa_bit() argument
78 if (enabled) { in riscv_cpu_write_misa_bit()
174 /* With Zfinx, floating point is enabled/disabled by Smstateen. */ in riscv_get_tb_cpu_state()
342 * All other named features are already enabled in riscv_cpu_enable_named_feat()
446 * These two extensions are always enabled as they were supported in riscv_cpu_disable_priv_spec_isa_exts()
873 if (!profile->enabled || !parent) { in riscv_cpu_check_parent_profile()
879 profile->enabled = parent_enabled; in riscv_cpu_check_parent_profile()
887 bool send_warn = profile->user_set && profile->enabled; in riscv_cpu_validate_profile()
940 profile->enabled = profile_impl; in riscv_cpu_validate_profile()
969 rule->enabled = bitmap_new(ms->smp.cpus); in riscv_cpu_init_implied_exts_rules()
[all …]
/qemu/target/arm/
H A Dcpu64.c42 * If any vector lengths are explicitly enabled with sve<N> properties, in arm_cpu_sve_finalize()
47 * are enabled and sve-max-vq is not specified, then all lengths not in arm_cpu_sve_finalize()
48 * explicitly disabled will be enabled. Additionally, all power-of-two in arm_cpu_sve_finalize()
49 * vector lengths less than the maximum enabled length will be in arm_cpu_sve_finalize()
50 * automatically enabled and all vector lengths larger than the largest in arm_cpu_sve_finalize()
54 * vector length must be enabled. in arm_cpu_sve_finalize()
64 * enabled by default. Attempting to enable any vector length not set in arm_cpu_sve_finalize()
65 * in the supported bitmap results in an error. When KVM is enabled we in arm_cpu_sve_finalize()
83 * Check first for any sve<N> enabled. in arm_cpu_sve_finalize()
105 /* Propagate enabled bits down through required powers-of-two. */ in arm_cpu_sve_finalize()
[all …]
/qemu/hw/i2c/
H A Di2c_mux_pca954x.c45 bool enabled[PCA9548_CHANNEL_COUNT]; member
65 * For each channel, if it's enabled, recursively call match on those children. in OBJECT_DECLARE_TYPE()
75 /* They are talking to the mux itself (or all devices enabled). */ in OBJECT_DECLARE_TYPE()
86 if (!mux->enabled[i]) { in OBJECT_DECLARE_TYPE()
113 s->enabled[i] = true; in pca954x_enable_channel()
115 s->enabled[i] = false; in pca954x_enable_channel()
209 s->enabled[i] = false; in pca954x_init()
/qemu/hw/i386/
H A Damd_iommu.h251 /* Interrupt remapping table fields (Guest VAPIC not enabled) */
267 /* Interrupt remapping table fields (Guest VAPIC is enabled) */
325 bool enabled; /* IOMMU enabled */ member
326 bool ats_enabled; /* address translation enabled */
327 bool cmdbuf_enabled; /* command buffer enabled */
328 bool evtlog_enabled; /* event log enabled */
350 bool excl_enable; /* exclusion range enabled */
/qemu/include/io/
H A Dchannel.h131 bool enabled,
149 bool enabled);
151 bool enabled);
505 * @enabled: the blocking flag state
508 * If @enabled is true, then the channel is put into
516 bool enabled,
522 * @enabled: whether or not to follow the coroutine's AioContext
524 * If @enabled is true, calls to qio_channel_yield() use the current
527 * If @enabled is false, calls to qio_channel_yield() use the global iohandler
532 void qio_channel_set_follow_coroutine_ctx(QIOChannel *ioc, bool enabled);
[all …]

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