Searched +full:emc +full:- +full:timings +full:- +full:0 (Results 1 – 19 of 19) sorted by relevance
/linux-5.10/drivers/memory/tegra/ |
D | tegra210-emc-table.c | 1 // SPDX-License-Identifier: GPL-2.0 8 #include "tegra210-emc.h" 15 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_table_device_init() local 16 struct tegra210_emc_timing *timings; in tegra210_emc_table_device_init() local 17 unsigned int i, count = 0; in tegra210_emc_table_device_init() 19 timings = memremap(rmem->base, rmem->size, MEMREMAP_WB); in tegra210_emc_table_device_init() 20 if (!timings) { in tegra210_emc_table_device_init() 21 dev_err(dev, "failed to map EMC table\n"); in tegra210_emc_table_device_init() 22 return -ENOMEM; in tegra210_emc_table_device_init() 25 count = 0; in tegra210_emc_table_device_init() [all …]
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D | tegra20-emc.c | 1 // SPDX-License-Identifier: GPL-2.0 24 #define EMC_INTSTATUS 0x000 25 #define EMC_INTMASK 0x004 26 #define EMC_DBG 0x008 27 #define EMC_TIMING_CONTROL 0x028 28 #define EMC_RC 0x02c 29 #define EMC_RFC 0x030 30 #define EMC_RAS 0x034 31 #define EMC_RP 0x038 32 #define EMC_R2W 0x03c [all …]
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D | tegra30-emc.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Based on downstream driver from NVIDIA and tegra124-emc.c 6 * Copyright (C) 2011-2014 NVIDIA Corporation 9 * Copyright (C) 2019 GRATE-DRIVER project 31 #define EMC_INTSTATUS 0x000 32 #define EMC_INTMASK 0x004 33 #define EMC_DBG 0x008 34 #define EMC_CFG 0x00c 35 #define EMC_REFCTRL 0x020 36 #define EMC_TIMING_CONTROL 0x028 [all …]
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D | tegra210-emc-core.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. 21 #include "tegra210-emc.h" 22 #include "tegra210-mc.h" 27 (0x7 << EMC_CLK_EMC_2X_CLK_SRC_SHIFT) 28 #define EMC_CLK_SOURCE_PLLM_LJ 0x4 29 #define EMC_CLK_SOURCE_PLLMB_LJ 0x5 32 #define EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT 0 34 (0xff << EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT) 39 (0x7 << DLL_CLK_EMC_DLL_CLK_SRC_SHIFT) [all …]
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D | tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #include <linux/clk-provider.h> 21 #include <soc/tegra/emc.h> 25 #define EMC_FBIO_CFG5 0x104 26 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3 27 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0 29 #define EMC_INTSTATUS 0x0 32 #define EMC_CFG 0xc 37 #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18)) 40 #define EMC_REFCTRL 0x20 [all …]
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D | tegra210-emc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. 21 #define EMC_INTSTATUS 0x0 23 #define EMC_DBG 0x8 26 #define EMC_CFG 0xc 31 #define EMC_PIN 0x24 32 #define EMC_PIN_PIN_CKE BIT(0) 35 #define EMC_TIMING_CONTROL 0x28 36 #define EMC_RC 0x2c 37 #define EMC_RFC 0x30 [all …]
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/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
D | nvidia,tegra124-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 The EMC interfaces with the off-chip SDRAM to service the request stream 19 const: nvidia,tegra124-emc 26 - description: external memory clock 28 clock-names: [all …]
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D | nvidia,tegra30-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dmitry Osipenko <digetx@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Thierry Reding <thierry.reding@gmail.com> 15 The EMC interfaces with the off-chip SDRAM to service the request stream 16 sent from Memory Controller. The EMC also has various performance-affecting 18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2, [all …]
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D | nvidia,tegra124-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Jon Hunter <jonathanh@nvidia.com> 11 - Thierry Reding <thierry.reding@gmail.com> 14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller. 22 const: nvidia,tegra124-mc 30 clock-names: 32 - const: mc [all …]
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D | nvidia,tegra30-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dmitry Osipenko <digetx@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Thierry Reding <thierry.reding@gmail.com> 39 const: nvidia,tegra30-mc 47 clock-names: 49 - const: mc [all …]
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/linux-5.10/drivers/clk/tegra/ |
D | clk-tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * drivers/clk/tegra/clk-emc.c 11 #include <linux/clk-provider.h> 24 #include <soc/tegra/emc.h> 28 #define CLK_SOURCE_EMC 0x19c 30 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0 31 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff 36 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7 46 * List of clock sources for various parents the EMC clock can have. 52 #define EMC_SRC_PLL_M 0 [all …]
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D | clk-tegra210-emc.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. 8 #include <linux/clk-provider.h> 17 #define CLK_SOURCE_EMC 0x19c 20 #define CLK_SOURCE_EMC_2X_CLK_DIVISOR GENMASK(7, 0) 22 #define CLK_SRC_PLLM 0 53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local 57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent() 66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local 71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate() [all …]
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/linux-5.10/Documentation/devicetree/bindings/clock/ |
D | nvidia,tegra124-car.txt | 4 Documentation/devicetree/bindings/clock/clock-bindings.txt 10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car" 11 - reg : Should contain CAR registers location and length 12 - clocks : Should contain phandle and clock specifiers for two clocks: 13 the 32 KHz "32k_in", and the board-specific oscillator "osc". 14 - #clock-cells : Should be 1. 17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common 18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h> 19 (for Tegra124-specific clocks). 20 - #reset-cells : Should be 1. [all …]
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/linux-5.10/arch/arm/boot/dts/ |
D | tegra30-asus-nexus7-tilapia-memory-timings.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi" 7 * Tilapia's memory timings are pretty much the same as the Grouper's 9 * these differentiating timings are overridden here for Tilapia. 12 memory-controller@7000f400 { 13 emc-timings-0 { 14 timing-667000000 { 15 clock-frequency = <667000000>; 17 nvidia,emc-auto-cal-interval = <0x001fffff>; 18 nvidia,emc-mode-1 = <0x80100002>; [all …]
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D | tegra124-nyan-blaze-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 emc-timings-1 { 5 nvidia,ram-code = <1>; 7 timing-12750000 { 8 clock-frequency = <12750000>; 9 nvidia,parent-clock-frequency = <408000000>; 11 clock-names = "emc-parent"; 13 timing-20400000 { 14 clock-frequency = <20400000>; 15 nvidia,parent-clock-frequency = <408000000>; [all …]
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D | tegra124-apalis-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR X11 3 * Copyright 2016-2019 Toradex AG 9 emc-timings-1 { 10 nvidia,ram-code = <1>; 12 timing-12750000 { 13 clock-frequency = <12750000>; 14 nvidia,parent-clock-frequency = <408000000>; 16 clock-names = "emc-parent"; 18 timing-20400000 { 19 clock-frequency = <20400000>; [all …]
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D | tegra124-jetson-tk1-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 emc-timings-3 { 5 nvidia,ram-code = <3>; 7 timing-12750000 { 8 clock-frequency = <12750000>; 9 nvidia,parent-clock-frequency = <408000000>; 11 clock-names = "emc-parent"; 13 timing-20400000 { 14 clock-frequency = <20400000>; 15 nvidia,parent-clock-frequency = <408000000>; [all …]
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D | tegra30-asus-nexus7-grouper-memory-timings.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 memory-controller@7000f000 { 5 emc-timings-0 { 6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */ 8 timing-25500000 { 9 clock-frequency = <25500000>; 11 nvidia,emem-configuration = < 12 0x00020001 /* MC_EMEM_ARB_CFG */ 13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */ 14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ [all …]
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D | tegra124-nyan-big-emc.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 nvidia,long-ram-code; 8 emc-timings-1 { 9 nvidia,ram-code = <1>; 11 timing-12750000 { 12 clock-frequency = <12750000>; 13 nvidia,parent-clock-frequency = <408000000>; 15 clock-names = "emc-parent"; 17 timing-20400000 { 18 clock-frequency = <20400000>; [all …]
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