Lines Matching +full:emc +full:- +full:timings +full:- +full:0
1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
39 const: nvidia,tegra30-mc
47 clock-names:
49 - const: mc
54 "#reset-cells":
57 "#iommu-cells":
61 "^emc-timings-[0-9]+$":
64 nvidia,ram-code:
70 "^timing-[0-9]+$":
73 clock-frequency:
79 nvidia,emem-configuration:
80 $ref: /schemas/types.yaml#/definitions/uint32-array
85 - description: MC_EMEM_ARB_CFG
86 - description: MC_EMEM_ARB_OUTSTANDING_REQ
87 - description: MC_EMEM_ARB_TIMING_RCD
88 - description: MC_EMEM_ARB_TIMING_RP
89 - description: MC_EMEM_ARB_TIMING_RC
90 - description: MC_EMEM_ARB_TIMING_RAS
91 - description: MC_EMEM_ARB_TIMING_FAW
92 - description: MC_EMEM_ARB_TIMING_RRD
93 - description: MC_EMEM_ARB_TIMING_RAP2PRE
94 - description: MC_EMEM_ARB_TIMING_WAP2PRE
95 - description: MC_EMEM_ARB_TIMING_R2R
96 - description: MC_EMEM_ARB_TIMING_W2W
97 - description: MC_EMEM_ARB_TIMING_R2W
98 - description: MC_EMEM_ARB_TIMING_W2R
99 - description: MC_EMEM_ARB_DA_TURNS
100 - description: MC_EMEM_ARB_DA_COVERS
101 - description: MC_EMEM_ARB_MISC0
102 - description: MC_EMEM_ARB_RING1_THROTTLE
105 - clock-frequency
106 - nvidia,emem-configuration
111 - nvidia,ram-code
116 - compatible
117 - reg
118 - interrupts
119 - clocks
120 - clock-names
121 - "#reset-cells"
122 - "#iommu-cells"
127 - |
128 memory-controller@7000f000 {
129 compatible = "nvidia,tegra30-mc";
130 reg = <0x7000f000 0x400>;
132 clock-names = "mc";
134 interrupts = <0 77 4>;
136 #iommu-cells = <1>;
137 #reset-cells = <1>;
139 emc-timings-1 {
140 nvidia,ram-code = <1>;
142 timing-667000000 {
143 clock-frequency = <667000000>;
145 nvidia,emem-configuration = <
146 0x0000000a /* MC_EMEM_ARB_CFG */
147 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
148 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
149 0x00000004 /* MC_EMEM_ARB_TIMING_RP */
150 0x00000010 /* MC_EMEM_ARB_TIMING_RC */
151 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
152 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
153 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
154 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
155 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
156 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
157 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
158 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
159 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
160 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
161 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */
162 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */
163 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */