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Searched +full:emc +full:- +full:mode +full:- +full:reset (Results 1 – 25 of 35) sorted by relevance

12

/linux-5.10/arch/arm/boot/dts/
Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-1 {
5 nvidia,ram-code = <1>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
9 emc-timings-1 {
10 nvidia,ram-code = <1>;
12 timing-12750000 {
13 clock-frequency = <12750000>;
14 nvidia,parent-clock-frequency = <408000000>;
16 clock-names = "emc-parent";
18 timing-20400000 {
19 clock-frequency = <20400000>;
[all …]
Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-3 {
5 nvidia,ram-code = <3>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
Dtegra30-asus-nexus7-grouper-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 memory-controller@7000f000 {
5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
8 timing-25500000 {
9 clock-frequency = <25500000>;
11 nvidia,emem-configuration = <
33 timing-51000000 {
34 clock-frequency = <51000000>;
36 nvidia,emem-configuration = <
[all …]
Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
12 memory-controller@7000f400 {
13 emc-timings-0 {
14 timing-667000000 {
15 clock-frequency = <667000000>;
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
[all …]
Dtegra124-nyan-big-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 nvidia,long-ram-code;
8 emc-timings-1 {
9 nvidia,ram-code = <1>;
11 timing-12750000 {
12 clock-frequency = <12750000>;
13 nvidia,parent-clock-frequency = <408000000>;
15 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]
Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra20-cpu-opp.dtsi"
10 #include "tegra20-cpu-opp-microvolt.dtsi"
31 * pre-existing /chosen node to be available to insert the
40 reserved-memory {
41 #address-cells = <1>;
[all …]
Dtegra20-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0
22 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
23 nvidia,hpd-gpio =
25 pll-supply = <&reg_1v8_avdd_hdmi_pll>;
26 vdd-supply = <&reg_3v3_avdd_hdmi>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&state_default>;
35 /* Analogue Audio AC97 to WM9712 (On-module) */
36 audio-refclk {
51 * (All on-module), SODIMM Pin 45 Wakeup
[all …]
Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "tegra20-cpu-opp.dtsi"
7 #include "tegra20-cpu-opp-microvolt.dtsi"
21 stdout-path = "serial0:115200n8";
40 vdd-supply = <&hdmi_vdd_reg>;
41 pll-supply = <&hdmi_pll_reg>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
44 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
[all …]
Dtegra20-seaboard.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
37 vdd-supply = <&hdmi_vdd_reg>;
38 pll-supply = <&hdmi_pll_reg>;
39 hdmi-supply = <&vdd_hdmi>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
[all …]
Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
13 interrupt-parent = <&lic>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
26 - description: external memory clock
28 clock-names:
[all …]
Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
[all …]
/linux-5.10/drivers/memory/tegra/
Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
357 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
364 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
368 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
377 struct tegra_emc *emc = data; in tegra_emc_isr() local
381 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
[all …]
Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
21 #include <soc/tegra/emc.h>
488 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
495 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
500 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
503 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
509 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
[all …]
Dtegra210-emc-cc-r21021.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
14 #include "tegra210-emc.h"
15 #include "tegra210-mc.h"
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) argument
53 * PTFV defines - basically just indexes into the per table PTFV array.
78 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] = \
79 next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] / \
80 next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
86 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] += \
[all …]
/linux-5.10/drivers/devfreq/
Dtegra20-devfreq.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 GRATE-DRIVER project
41 struct devfreq *devfreq = tegra->devfreq; in tegra_devfreq_target()
53 err = clk_set_min_rate(tegra->emc_clock, rate); in tegra_devfreq_target()
57 err = clk_set_rate(tegra->emc_clock, 0); in tegra_devfreq_target()
64 clk_set_min_rate(tegra->emc_clock, devfreq->previous_freq); in tegra_devfreq_target()
84 stat->busy_time = readl_relaxed(tegra->regs + MC_STAT_EMC_COUNT); in tegra_devfreq_get_dev_status()
85 stat->total_time = readl_relaxed(tegra->regs + MC_STAT_EMC_CLOCKS) / 8; in tegra_devfreq_get_dev_status()
86 stat->current_frequency = clk_get_rate(tegra->emc_clock); in tegra_devfreq_get_dev_status()
88 writel_relaxed(EMC_GATHER_CLEAR, tegra->regs + MC_STAT_CONTROL); in tegra_devfreq_get_dev_status()
[all …]
/linux-5.10/arch/s390/include/uapi/asm/
Ddasd.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
6 * EMC Symmetrix ioctl Copyright EMC Corporation, 2008
7 * Author.........: Nigel Hislop <hislop_nigel@emc.com>
11 * to userspace by the DASDAPIVER-ioctl
121 * Read Subsystem Data - Performance Statistics
222 /* Blocksize/data-length of a record was wrong */
227 /* If key-length was != 0 */
236 unsigned char operation:3; /* cache operation mode */
237 unsigned char reserved:5; /* cache operation mode */
251 * Perform EMC Symmetrix I/O
[all …]
/linux-5.10/arch/arm/mach-tegra/
Dsleep-tegra30.S1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/asm-offsets.h>
143 * Puts the current CPU in wait-for-event mode on the flow controller
144 * and powergates it -- flags (in R0) indicate the request type.
147 * corrupts r0-r4, r10-r12
244 * CPU power-gating process, to avoid loading from SDRAM which
245 * are not supported once SDRAM is put into self-refresh.
247 * disabled before putting SDRAM into self-refresh to avoid
280 mov r0, #0 @ power mode flags (!hotplug)
305 * reset vector for LP1 restore; copied into IRAM during suspend.
[all …]
Dsleep-tegra20.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
15 #include <asm/proc-fns.h>
20 #include "reset.h"
64 * puts the current cpu in reset
77 * r0 is cpu to reset
79 * puts the specified CPU in wait-for-event mode on the flow controller
80 * and puts the CPU in reset
85 * corrupts r0-r3, r12
94 str r2, [r3, r1] @ put flow controller in wait event mode
[all …]
/linux-5.10/drivers/input/mouse/
Delan_i2c_i2c.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Elan I2C/SMBus Touchpad driver - I2C interface
7 * Author: 林政維 (Duson Lin) <dusonlin@emc.com.tw>
10 * copyright (c) 2011-2012 Cypress Semiconductor, Inc.
11 * copyright (c) 2011-2012 Google, Inc.
82 .addr = client->addr, in elan_i2c_read_block()
83 .flags = client->flags & I2C_M_TEN, in elan_i2c_read_block()
88 .addr = client->addr, in elan_i2c_read_block()
89 .flags = (client->flags & I2C_M_TEN) | I2C_M_RD, in elan_i2c_read_block()
96 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); in elan_i2c_read_block()
[all …]
Delan_i2c_smbus.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Elan I2C/SMBus Touchpad driver - SMBus interface
7 * Author: 林政維 (Duson Lin) <dusonlin@emc.com.tw>
10 * copyright (c) 2011-2012 Cypress Semiconductor, Inc.
11 * copyright (c) 2011-2012 Google, Inc.
63 dev_err(&client->dev, "hello packet length fail: %d\n", len); in elan_smbus_initialize()
64 error = len < 0 ? len : -EIO; in elan_smbus_initialize()
70 dev_err(&client->dev, "hello packet fail [%*ph]\n", in elan_smbus_initialize()
72 return -ENXIO; in elan_smbus_initialize()
78 dev_err(&client->dev, "failed to enable touchpad: %d\n", error); in elan_smbus_initialize()
[all …]
Delan_i2c_core.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Author: 林政維 (Duson Lin) <dusonlin@emc.com.tw>
8 * Author: KT Liao <kt.liao@emc.com.tw>
12 * copyright (c) 2011-2012 Cypress Semiconductor, Inc.
13 * copyright (c) 2011-2012 Google, Inc.
37 #include <linux/input/elan-i2c-ids.h>
93 u8 mode; member
149 return -ENXIO; in elan_get_fwinfo()
153 (*validpage_count * ETP_FW_PAGE_SIZE) - ETP_FW_SIGNATURE_SIZE; in elan_get_fwinfo()
173 error = regulator_enable(data->vcc); in elan_enable_power()
[all …]
/linux-5.10/Documentation/networking/device_drivers/wifi/intel/
Dipw2200.rst1 .. SPDX-License-Identifier: GPL-2.0
11 - Intel(R) PRO/Wireless 2200BG Network Connection
12 - Intel(R) PRO/Wireless 2915ABG Network Connection
20 Copyright |copy| 2004-2006, Intel Corporation
37 2. Ad-Hoc Networking
39 3.1. iwconfig mode
64 radio operation and to ensure electromagnetic compliance (EMC). These
78 the warranty and/or issues arising from regulatory non-compliance, and
83 modules, and accordingly, condition system-level regulatory approval
85 system configuration do not cause the EMC and radio operation to be
[all …]
/linux-5.10/drivers/input/touchscreen/
Delants_i2c.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Scott Liu <scott.liu@emc.com.tw>
8 * This code is partly based on hid-multitouch.c:
10 * Copyright (c) 2010-2012 Stephane Chatty <chatty@enac.fr>
11 * Copyright (c) 2010-2012 Benjamin Tissoires <benjamin.tissoires@gmail.com>
12 * Copyright (c) 2010-2012 Ecole Nationale de l'Aviation Civile, France
14 * This code is partly based on i2c-hid.c:
47 #define ELAN_TS_RESOLUTION(n, m) (((n) - 1) * (m))
55 /* Buffer mode Queue Header information */
85 /* Header (4 bytes) plus 3 fill 10-finger packets */
[all …]

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