Lines Matching +full:emc +full:- +full:mode +full:- +full:reset

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
15 #include <asm/proc-fns.h>
20 #include "reset.h"
64  * puts the current cpu in reset
77  * r0 is cpu to reset
79  * puts the specified CPU in wait-for-event mode on the flow controller
80  * and puts the CPU in reset
85  * corrupts r0-r3, r12
94 	str	r2, [r3, r1]		@ put flow controller in wait event mode
101 	str	r1, [r3, #0x340]	@ put slave CPU in reset
140  * Switches the CPU cluster to PLL-P and enters sleep.
155  * reset vector for LP1 restore; copied into IRAM during suspend.
157  * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLP,
242  * puts memory in self-refresh for LP0 and LP1
322 	mov32	r1, TEGRA_EMC_BASE	@ r1 reserved for emc base addr
341 	bne	emcself			@ loop until DDR in self-refresh
380 	.word	tegra20_sdram_pad_size - tegra20_sdram_pad_address
395 	.rept (tegra20_sdram_pad_size - tegra20_sdram_pad_address) / 4