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Searched +full:dsi +full:- +full:pclk (Results 1 – 25 of 75) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A Dvlv_dsi_pll.c42 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
43 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
44 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
45 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
48 /* Get DSI clock from pixel clock */
49 static u32 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt, in dsi_clk_from_pclk() argument
55 /* DSI data rate = pixel clock * bits per pixel / lane count in dsi_clk_from_pclk()
57 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
73 drm_err(display->drm, "DSI CLK Out of Range\n"); in dsi_calc_mnp()
74 return -ECHRNG; in dsi_calc_mnp()
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H A Dintel_dsi_vbt.c68 /* ICL DSI Display GPIO Pins */
84 * If single link DSI is being used on any port, the VBT sequence block in intel_dsi_seq_port_to_port()
88 if (hweight8(intel_dsi->ports) == 1) in intel_dsi_seq_port_to_port()
89 return ffs(intel_dsi->ports) - 1; in intel_dsi_seq_port_to_port()
92 if (intel_dsi->ports & BIT(PORT_B)) in intel_dsi_seq_port_to_port()
94 if (intel_dsi->ports & BIT(PORT_C)) in intel_dsi_seq_port_to_port()
104 struct intel_display *display = to_intel_display(&intel_dsi->base); in mipi_exec_send_packet()
110 drm_dbg_kms(display->drm, "\n"); in mipi_exec_send_packet()
122 if (drm_WARN_ON(display->drm, !intel_dsi->dsi_hosts[port])) in mipi_exec_send_packet()
125 dsi_device = intel_dsi->dsi_hosts[port]->device; in mipi_exec_send_packet()
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H A Dvlv_dsi.c91 struct intel_display *display = to_intel_display(&intel_dsi->base); in vlv_dsi_wait_for_fifo_empty()
99 drm_err(display->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
111 for (j = 0; j < min_t(u32, len - i, 4); j++) in write_data()
127 for (j = 0; j < min_t(u32, len - i, 4); j++) in read_data()
136 struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi; in intel_dsi_host_transfer()
137 struct intel_display *display = to_intel_display(&intel_dsi->base); in intel_dsi_host_transfer()
138 enum port port = intel_dsi_host->port; in intel_dsi_host_transfer()
151 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { in intel_dsi_host_transfer()
167 drm_err(display->drm, in intel_dsi_host_transfer()
174 if (msg->rx_len) { in intel_dsi_host_transfer()
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/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,dw-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
16 - enum:
17 - rockchip,px30-mipi-dsi
18 - rockchip,rk3128-mipi-dsi
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H A Drockchip,rk3588-mipi-dsi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3588-mipi-dsi2
26 clock-names:
28 - const: pclk
29 - const: sys
39 phy-names:
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/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mm-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
20 - const: fsl,imx8mm-disp-blk-ctrl
21 - const: syscon
26 '#power-domain-cells':
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H A Dfsl,imx8mn-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MN DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
20 - const: fsl,imx8mn-disp-blk-ctrl
21 - const: syscon
26 '#power-domain-cells':
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/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
17 #include <linux/media-bus-format.h>
197 #define N_LANES(n) (((n) - 1) & 0x3)
230 #define VPG_DEFS(name, dsi) \ argument
231 ((void __force *)&((*dsi).vpg_defs.name))
233 #define REGISTER(name, mask, dsi) \ argument
234 { #name, VPG_DEFS(name, dsi), mask, dsi }
240 struct dw_mipi_dsi *dsi; member
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/linux/drivers/gpu/drm/hisilicon/kirin/
H A Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DesignWare MIPI DSI Host Controller v1.02 driver
6 * Copyright (c) 2014-2016 HiSilicon Limited.
80 struct clk *pclk; member
98 struct dw_dsi dsi; member
152 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
153 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
155 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
156 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
157 q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); in dsi_calc_phy_rate()
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L MIPI DSI Encoder
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This binding describes the MIPI DSI encoder embedded in the Renesas
14 RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
18 - $ref: /schemas/display/dsi-controller.yaml#
23 - enum:
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H A Dnwl-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
10 - Guido Gúnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com>
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
18 - $ref: ../dsi-controller.yaml#
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H A Dcdns,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/cdns,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence DSI bridge
10 - Boris Brezillon <boris.brezillon@bootlin.com>
13 CDNS DSI is a bridge device which converts DPI to DSI
18 - cdns,dsi
19 - ti,j721e-dsi
24 - description:
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/linux/Documentation/devicetree/bindings/display/hisilicon/
H A Ddw-dsi.txt1 Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
3 A DSI Host Controller resides in the middle of display controller and external
7 - compatible: value should be "hisilicon,hi6220-dsi".
8 - reg: physical base address and length of dsi controller's registers.
9 - clocks: contains APB clock phandle + clock-specifier pair.
10 - clock-names: should be "pclk".
11 - ports: contains DSI controller input and output sub port.
21 dsi: dsi@f4107800 {
22 compatible = "hisilicon,hi6220-dsi";
25 clock-names = "pclk";
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/linux/drivers/gpu/drm/rockchip/
H A Ddw-mipi-dsi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
269 struct clk *pclk; member
274 /* dual-channel */
365 return -EINVAL; in max_mbps_to_parameter()
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/linux/Documentation/devicetree/bindings/phy/
H A Drockchip,px30-dsi-dphy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
13 "#phy-cells":
18 - rockchip,px30-dsi-dphy
19 - rockchip,rk3128-dsi-dphy
20 - rockchip,rk3368-dsi-dphy
21 - rockchip,rk3568-dsi-dphy
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/linux/Documentation/devicetree/bindings/display/
H A Damlogic,meson-g12a-dw-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-g12a-dw-mipi-dsi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 - A Synopsys DesignWare MIPI DSI Host Controller IP
16 - A TOP control block controlling the Clocks & Resets of the IP
19 - $ref: dsi-controller.yaml#
24 - amlogic,meson-g12a-dw-mipi-dsi
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H A Dst,stm32-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DSI host controller
10 - Philippe Cornu <philippe.cornu@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
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H A Drenesas,rzg2l-du.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
20 - enum:
21 - renesas,r9a07g043u-du # RZ/G2UL
22 - renesas,r9a07g044-du # RZ/G2{L,LC}
23 - renesas,r9a09g057-du # RZ/V2H(P)
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/linux/arch/arm/boot/dts/st/
H A Dstm32f469.dtsi1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */
8 dsi: dsi@40016c00 { label
9 compatible = "st,stm32-dsi";
11 resets = <&rcc STM32F4_APB2_RESET(DSI)>;
12 reset-names = "apb";
14 clock-names = "pclk", "ref";
H A Dstm32mp157.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
16 clock-names = "bus" ,"core";
20 dsi: dsi@5a000000 { label
21 compatible = "st,stm32-dsi";
23 clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>;
24 clock-names = "pclk", "ref", "px_clk";
25 phy-dsi-supply = <&reg18>;
27 reset-names = "apb";
31 #address-cells = <1>;
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H A Dstm32f769.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "st,stm32f4-bxcan";
14 interrupt-names = "tx", "rx0", "rx1", "sce";
22 compatible = "st,stm32f4-gcan", "syscon";
27 dsi: dsi@40016c00 { label
28 compatible = "st,stm32-dsi";
31 clock-names = "pclk", "ref";
32 resets = <&rcc STM32F7_APB2_RESET(DSI)>;
33 reset-names = "apb";
/linux/drivers/gpu/drm/bridge/
H A Dlontium-lt9611.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2019-2020. Linaro Limited.
10 #include <linux/media-bus-format.h>
17 #include <sound/hdmi-codec.h>
104 { 0x811c, 0x03 }, /* PortA clk lane no-LP mode */ in lt9611_mipi_input_analog()
105 { 0x8120, 0x03 }, /* PortB clk lane with-LP mode */ in lt9611_mipi_input_analog()
108 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_analog()
123 if (lt9611->dsi1_node) in lt9611_mipi_input_digital()
126 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_digital()
135 h_total = mode->htotal; in lt9611_mipi_video_setup()
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H A Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX8 NWL MIPI DSI host driver
15 #include <linux/media-bus-format.h>
34 #include "nwl-dsi.h"
36 #define DRV_NAME "nwl-dsi"
77 * The DSI host controller needs this reset sequence according to NWL:
78 * 1. Deassert pclk reset to get access to DSI regs
79 * 2. Configure DSI Host and DPHY and enable DPHY
81 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
83 * DSI data
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H A Dtc358768.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
13 #include <linux/media-bus-format.h>
29 /* Global (16-bit addressable) */
46 /* Debug (16-bit addressable) */
52 /* TX PHY (32-bit addressable) */
64 /* TX PPI (32-bit addressable) */
80 /* TX CTRL (32-bit addressable) */
101 /* DSITX CTRL (16-bit addressable) */
155 u32 dsi_lanes; /* number of DSI Lanes */
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/linux/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4_kms.c1 // SPDX-License-Identifier: GPL-2.0-only
21 struct drm_device *dev = mdp4_kms->dev; in mdp4_hw_init()
25 pm_runtime_get_sync(dev->dev); in mdp4_hw_init()
27 if (mdp4_kms->rev > 1) { in mdp4_hw_init()
37 clk = clk_get_rate(mdp4_kms->clk); in mdp4_hw_init()
39 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) { in mdp4_hw_init()
40 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */ in mdp4_hw_init()
41 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */ in mdp4_hw_init()
43 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */ in mdp4_hw_init()
44 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */ in mdp4_hw_init()
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