xref: /linux/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml (revision 74f1af95820fc2ee580a775a3a17c416db30b38c)

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Northwest Logic MIPI-DSI controller on i.MX SoCs

maintainers:
  - Guido Gúnther <agx@sigxcpu.org>
  - Robert Chiras <robert.chiras@nxp.com>

description: |
  NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
  the SOCs NWL MIPI-DSI host controller.

allOf:
  - $ref: ../dsi-controller.yaml#

properties:
  compatible:
    const: fsl,imx8mq-nwl-dsi

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

  assigned-clock-parents: true
  assigned-clock-rates: true
  assigned-clocks: true

  clocks:
    items:
      - description: DSI core clock
      - description: RX_ESC clock (used in escape mode)
      - description: TX_ESC clock (used in escape mode)
      - description: PHY_REF clock
      - description: LCDIF clock

  clock-names:
    items:
      - const: core
      - const: rx_esc
      - const: tx_esc
      - const: phy_ref
      - const: lcdif

  mux-controls:
    description:
      mux controller node to use for operating the input mux

  phys:
    maxItems: 1
    description:
      A phandle to the phy module representing the DPHY

  phy-names:
    items:
      - const: dphy

  power-domains:
    maxItems: 1

  resets:
    items:
      - description: dsi byte reset line
      - description: dsi dpi reset line
      - description: dsi esc reset line
      - description: dsi pclk reset line

  reset-names:
    items:
      - const: byte
      - const: dpi
      - const: esc
      - const: pclk

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        description:
          Input port node to receive pixel data from the
          display controller. Exactly one endpoint must be
          specified.
        properties:
          endpoint@0:
            $ref: /schemas/graph.yaml#/properties/endpoint
            description: sub-node describing the input from LCDIF

          endpoint@1:
            $ref: /schemas/graph.yaml#/properties/endpoint
            description: sub-node describing the input from DCSS

        oneOf:
          - required:
              - endpoint@0
          - required:
              - endpoint@1

        unevaluatedProperties: false

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          DSI output port node to the panel or the next bridge
          in the chain

        properties:
          endpoint:
            $ref: /schemas/media/video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                description: array of physical DSI data lane indexes.
                minItems: 1
                items:
                  - const: 1
                  - const: 2
                  - const: 3
                  - const: 4

    required:
      - port@0
      - port@1

required:
  - '#address-cells'
  - '#size-cells'
  - clock-names
  - clocks
  - compatible
  - interrupts
  - mux-controls
  - phy-names
  - phys
  - ports
  - reg
  - reset-names
  - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx8mq-clock.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/reset/imx8mq-reset.h>

    dsi@30a00000 {
              #address-cells = <1>;
              #size-cells = <0>;
              compatible = "fsl,imx8mq-nwl-dsi";
              reg = <0x30A00000 0x300>;
              clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
                       <&clk IMX8MQ_CLK_DSI_AHB>,
                       <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
                       <&clk IMX8MQ_CLK_DSI_PHY_REF>,
                       <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
              clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
              interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
              mux-controls = <&mux 0>;
              power-domains = <&pgc_mipi>;
              resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
                       <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
                       <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
                       <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
              reset-names = "byte", "dpi", "esc", "pclk";
              phys = <&dphy>;
              phy-names = "dphy";

              panel@0 {
                      compatible = "rocktech,jh057n00900";
                      reg = <0>;
                      vcc-supply = <&reg_2v8_p>;
                      iovcc-supply = <&reg_1v8_p>;
                      reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
                      port {
                           panel_in: endpoint {
                                     remote-endpoint = <&mipi_dsi_out>;
                           };
                      };
              };

              ports {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    port@0 {
                           #size-cells = <0>;
                           #address-cells = <1>;
                           reg = <0>;
                           mipi_dsi_in: endpoint@0 {
                                        reg = <0>;
                                        remote-endpoint = <&lcdif_mipi_dsi>;
                           };
                    };
                    port@1 {
                           reg = <1>;
                           mipi_dsi_out: endpoint {
                                         remote-endpoint = <&panel_in>;
                           };
                    };
              };
    };