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/qemu/docs/interop/
H A Dqmp-spec.rst384 Downstream extension of QMP
387 We recommend that downstream consumers of QEMU do *not* modify QMP.
388 Management tools should be able to support both upstream and downstream
389 versions of QMP without special logic, and downstream extensions are
393 avoid modifying QMP. Both upstream and downstream need to take care to
397 ``__`` (double underscore) for downstream use ("downstream names"). This
398 means upstream will never use any downstream names for its commands,
401 Any new names downstream wishes to add must begin with ``__``. To
403 recommended that you prefix your downstream names with ``__RFQDN_`` where
411 Downstream must not change the `server greeting`_ other than
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/qemu/hw/misc/
H A Dtz-msc.c242 const char *name = "tz-msc-downstream"; in tz_msc_realize()
247 * as we don't know the size of the MR used as the downstream until then. in tz_msc_realize()
248 * We insist on having a downstream, to avoid complicating the in tz_msc_realize()
250 * enough for the user to create an unimplemented_device as downstream in tz_msc_realize()
253 if (!s->downstream) { in tz_msc_realize()
254 error_setg(errp, "MSC 'downstream' link not set"); in tz_msc_realize()
262 size = memory_region_size(s->downstream); in tz_msc_realize()
263 address_space_init(&s->downstream_as, s->downstream, name); in tz_msc_realize()
282 DEFINE_PROP_LINK("downstream", TZMSC, downstream,
H A Dtz-mpc.c389 * blocking them; non-blocked accesses go directly to the downstream
502 * as we don't know the size of the MR used as the downstream until then. in tz_mpc_realize()
503 * We insist on having a downstream, to avoid complicating the code in tz_mpc_realize()
505 * enough for the user to create an unimplemented_device as downstream in tz_mpc_realize()
508 if (!s->downstream) { in tz_mpc_realize()
509 error_setg(errp, "MPC 'downstream' link not set"); in tz_mpc_realize()
513 size = memory_region_size(s->downstream); in tz_mpc_realize()
528 "MPC 'downstream' size %" PRId64 in tz_mpc_realize()
553 address_space_init(&s->downstream_as, s->downstream, in tz_mpc_realize()
554 "tz-mpc-downstream"); in tz_mpc_realize()
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H A Dtz-ppc.c249 * as we don't know the size of the MR used as the downstream until then. in tz_ppc_realize()
252 if (s->port[i].downstream) { in tz_ppc_realize()
262 if (!port->downstream) { in tz_ppc_realize()
279 address_space_init(&port->downstream_as, port->downstream, name); in tz_ppc_realize()
281 size = memory_region_size(port->downstream); in tz_ppc_realize()
305 DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \
/qemu/docs/
H A Dpcie.txt35 PCI Express Downstream ports.
88 Only use PCI Express Switches (x3130-upstream, xio3130-downstream)
107 | | Downstream Port | | Downstream Port | |
124 … -device xio3130-downstream,id=downstream_port1,bus=upstream_port1,chassis=x1,slot=y1[,addr=z1]] \
173 The PCI Express Root Ports and PCI Express Downstream ports are seen by
181 Downstream port if:
187 10 PCI Express Root Ports or PCI Express Downstream Ports per system
203 PCI Express Root Ports, PCI Express Downstream/Upstream ports)
205 can be attached to a PCI Express Root Port or PCI Express Downstream
230 Be aware that PCI Express Downstream Ports can't be hot-plugged into
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/qemu/include/hw/misc/
H A Dtz-ppc.h30 * port can be emulated simply by wiring its downstream devices directly
34 * In the hardware, selection of which downstream port to use is done by
42 * downstream MemoryRegion is connected to it) at the end of the 0..15
48 * + Property "port[0..15]": MemoryRegion defining the downstream device(s)
81 MemoryRegion *downstream; member
H A Dtz-mpc.h27 * + Property "downstream": MemoryRegion defining the downstream memory
64 MemoryRegion *downstream; member
H A Dtz-msc.h40 * + Property "downstream": MemoryRegion defining where bus master transactions
74 MemoryRegion *downstream; member
/qemu/include/hw/input/
H A Di8042.h45 * + Named GPIO input "ps2-kbd-input-irq": set to 1 if the downstream PS2
47 * + Named GPIO input "ps2-mouse-input-irq": set to 1 if the downstream PS2
70 * + Named GPIO input "ps2-kbd-input-irq": set to 1 if the downstream PS2
72 * + Named GPIO input "ps2-mouse-input-irq": set to 1 if the downstream PS2
H A Dlasips2.h15 * + Named GPIO input "lasips2-port-input-irq[0..1]": set to 1 if the downstream
/qemu/hw/arm/
H A Dmusca.c119 * needs to be plugged into the downstream end of the PPC port.
226 MemoryRegion *downstream; in make_mpc() local
236 downstream = &mms->ram[i]; in make_mpc()
237 memory_region_init_rom(downstream, NULL, mpcinfo[i].name, in make_mpc()
241 downstream = &mms->ram[i]; in make_mpc()
242 memory_region_init_ram(downstream, NULL, mpcinfo[i].name, in make_mpc()
253 downstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(uds), 0); in make_mpc()
260 object_property_set_link(OBJECT(mpc), "downstream", OBJECT(downstream), in make_mpc()
436 * + initialize, configure and realize downstream devices in musca_init()
437 * + connect downstream device MemoryRegions to the PPC in musca_init()
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/qemu/include/hw/pci-bridge/
H A Dxio3130_downstream.h2 * TI X3130 pci express downstream port switch
12 #define TYPE_XIO3130_DOWNSTREAM "xio3130-downstream"
/qemu/hw/pci-bridge/
H A Dxio3130_downstream.c3 * TI X3130 pci express downstream port switch
33 #define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */
143 .name = "xio3130-express-downstream-port",
168 dc->desc = "TI X3130 Downstream Port of PCI Express Switch"; in xio3130_downstream_class_init()
H A Dcxl_downstream.c2 * Emulated CXL Switch Downstream Port
232 k->device_id = 0xa129; /* Emulated CXL Switch Downstream Port */ in cxl_dsp_class_init()
235 dc->desc = "CXL Switch Downstream Port"; in cxl_dsp_class_init()
/qemu/docs/system/devices/
H A Dcxl.rst130 downstream ports.
132 Both the CXL upstream and downstream ports have CXL specific
136 appropriate downstream port.
140 downstream ports on the internal switch bus (cxl-downstream).
285 | appropriate downstream port |
377 -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4 \
379 -device cxl-downstream,port=1,bus=us0,id=swport1,chassis=0,slot=5 \
381 -device cxl-downstream,port=2,bus=us0,id=swport2,chassis=0,slot=6 \
383 -device cxl-downstream,port=3,bus=us0,id=swport3,chassis=0,slot=7 \
/qemu/include/hw/dma/
H A Dpl080.h25 * + QOM property "downstream": MemoryRegion defining where DMA
69 MemoryRegion *downstream; member
/qemu/hw/dma/
H A Dpl080.c396 if (!s->downstream) { in pl080_realize()
397 error_setg(errp, "PL080 'downstream' link not set"); in pl080_realize()
401 address_space_init(&s->downstream_as, s->downstream, "pl080-downstream"); in pl080_realize()
412 DEFINE_PROP_LINK("downstream", PL080State, downstream,
/qemu/hw/usb/
H A Dbus.c369 void usb_port_location(USBPort *downstream, USBPort *upstream, int portnr) in usb_port_location() argument
372 int l = snprintf(downstream->path, sizeof(downstream->path), "%s.%d", in usb_port_location()
375 assert(l < sizeof(downstream->path)); in usb_port_location()
376 downstream->hubcount = upstream->hubcount + 1; in usb_port_location()
378 snprintf(downstream->path, sizeof(downstream->path), "%d", portnr); in usb_port_location()
379 downstream->hubcount = 0; in usb_port_location()
H A Ddev-hub.c293 USBDevice *downstream; in usb_hub_find_device() local
301 downstream = usb_find_device(&port->port, addr); in usb_hub_find_device()
302 if (downstream != NULL) { in usb_hub_find_device()
303 return downstream; in usb_hub_find_device()
/qemu/hw/pci/
H A Dpcie.c193 * downstream ports supporting links wider than x1 or multiple link in pcie_cap_fill_slot_lnk()
204 * Hot-plug capable downstream ports and downstream ports supporting in pcie_cap_fill_slot_lnk()
666 /* pci express slot for pci express root/downstream port
761 /* Downstream ports enforce device number 0. */ in pcie_cap_slot_reset()
899 * Software issues a command to a hot-plug capable Downstream Port by in pcie_cap_slot_write_config()
969 * forwarding support for root and downstream ports
1090 * downstream device. If downstream device is not present, re-write with the
1091 * Link Capability fields. If downstream device reports invalid width or
1095 * to access the downstream device since it could be an assigned device with
1197 * Downstream ports must implement SV, TB, RR, CR, UF, and DT (with in pcie_acs_init()
/qemu/qapi/
H A Dqapi-util.c112 * It may be prefixed by __RFQDN_ (downstream extension), where RFQDN
124 if (*p == '_') { /* Downstream __RFQDN_ */ in parse_qapi_name()
H A Dcontrol.json82 # Downstream versions of QEMU should set this to a non-empty
83 # string. The exact format depends on the downstream however it
/qemu/tests/qapi-schema/
H A Dreserved-member-underscore.json3 # begin with a letter or a downstream extension double-underscore prefix).
/qemu/include/hw/cxl/
H A Dcxl.h65 #define TYPE_CXL_DSP "cxl-downstream"
H A Dcxl_component.h110 #define CXL_SEC_REGISTERS_SIZE 0 /* We don't implement 1.1 downstream ports */
238 * host bridges, root ports, upstream/downstream switch ports, and devices

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