xref: /qemu/hw/pci-bridge/xio3130_downstream.c (revision 06b40d250ecfa1633209c2e431a7a38acfd03a98)
148ebf2f9SIsaku Yamahata /*
248ebf2f9SIsaku Yamahata  * x3130_downstream.c
348ebf2f9SIsaku Yamahata  * TI X3130 pci express downstream port switch
448ebf2f9SIsaku Yamahata  *
548ebf2f9SIsaku Yamahata  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
648ebf2f9SIsaku Yamahata  *                    VA Linux Systems Japan K.K.
748ebf2f9SIsaku Yamahata  *
848ebf2f9SIsaku Yamahata  * This program is free software; you can redistribute it and/or modify
948ebf2f9SIsaku Yamahata  * it under the terms of the GNU General Public License as published by
1048ebf2f9SIsaku Yamahata  * the Free Software Foundation; either version 2 of the License, or
1148ebf2f9SIsaku Yamahata  * (at your option) any later version.
1248ebf2f9SIsaku Yamahata  *
1348ebf2f9SIsaku Yamahata  * This program is distributed in the hope that it will be useful,
1448ebf2f9SIsaku Yamahata  * but WITHOUT ANY WARRANTY; without even the implied warranty of
1548ebf2f9SIsaku Yamahata  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1648ebf2f9SIsaku Yamahata  * GNU General Public License for more details.
1748ebf2f9SIsaku Yamahata  *
1848ebf2f9SIsaku Yamahata  * You should have received a copy of the GNU General Public License along
1948ebf2f9SIsaku Yamahata  * with this program; if not, see <http://www.gnu.org/licenses/>.
2048ebf2f9SIsaku Yamahata  */
2148ebf2f9SIsaku Yamahata 
2297d5408fSPeter Maydell #include "qemu/osdep.h"
2383c9f4caSPaolo Bonzini #include "hw/pci/pci_ids.h"
2483c9f4caSPaolo Bonzini #include "hw/pci/msi.h"
2583c9f4caSPaolo Bonzini #include "hw/pci/pcie.h"
26c6329a2dSPhilippe Mathieu-Daudé #include "hw/pci/pcie_port.h"
27a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h"
28d6454270SMarkus Armbruster #include "migration/vmstate.h"
291108b2f8SCao jin #include "qapi/error.h"
300b8fa32fSMarkus Armbruster #include "qemu/module.h"
31c41481afSIgor Mammedov #include "hw/pci-bridge/xio3130_downstream.h"
3248ebf2f9SIsaku Yamahata 
3348ebf2f9SIsaku Yamahata #define PCI_DEVICE_ID_TI_XIO3130D       0x8233  /* downstream port */
3448ebf2f9SIsaku Yamahata #define XIO3130_REVISION                0x1
3548ebf2f9SIsaku Yamahata #define XIO3130_MSI_OFFSET              0x70
3648ebf2f9SIsaku Yamahata #define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
3748ebf2f9SIsaku Yamahata #define XIO3130_MSI_NR_VECTOR           1
3848ebf2f9SIsaku Yamahata #define XIO3130_SSVID_OFFSET            0x80
3948ebf2f9SIsaku Yamahata #define XIO3130_SSVID_SVID              0
4048ebf2f9SIsaku Yamahata #define XIO3130_SSVID_SSID              0
4148ebf2f9SIsaku Yamahata #define XIO3130_EXP_OFFSET              0x90
4248ebf2f9SIsaku Yamahata #define XIO3130_AER_OFFSET              0x100
4348ebf2f9SIsaku Yamahata 
xio3130_downstream_write_config(PCIDevice * d,uint32_t address,uint32_t val,int len)4448ebf2f9SIsaku Yamahata static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
4548ebf2f9SIsaku Yamahata                                          uint32_t val, int len)
4648ebf2f9SIsaku Yamahata {
472841ab43SMichael S. Tsirkin     uint16_t slt_ctl, slt_sta;
482841ab43SMichael S. Tsirkin 
498e2e95efSMichael S. Tsirkin     pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
5048ebf2f9SIsaku Yamahata     pci_bridge_write_config(d, address, val, len);
5148ebf2f9SIsaku Yamahata     pcie_cap_flr_write_config(d, address, val, len);
522841ab43SMichael S. Tsirkin     pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
5309b926d4SIsaku Yamahata     pcie_aer_write_config(d, address, val, len);
5448ebf2f9SIsaku Yamahata }
5548ebf2f9SIsaku Yamahata 
xio3130_downstream_reset(DeviceState * qdev)5648ebf2f9SIsaku Yamahata static void xio3130_downstream_reset(DeviceState *qdev)
5748ebf2f9SIsaku Yamahata {
5840021f08SAnthony Liguori     PCIDevice *d = PCI_DEVICE(qdev);
59cbd2d434SJan Kiszka 
6048ebf2f9SIsaku Yamahata     pcie_cap_deverr_reset(d);
6148ebf2f9SIsaku Yamahata     pcie_cap_slot_reset(d);
62821be9dbSKnut Omang     pcie_cap_arifwd_reset(d);
6348ebf2f9SIsaku Yamahata     pci_bridge_reset(qdev);
6448ebf2f9SIsaku Yamahata }
6548ebf2f9SIsaku Yamahata 
xio3130_downstream_realize(PCIDevice * d,Error ** errp)66f8cd1b02SMao Zhongyi static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
6748ebf2f9SIsaku Yamahata {
68bcb75750SAndreas Färber     PCIEPort *p = PCIE_PORT(d);
69bcb75750SAndreas Färber     PCIESlot *s = PCIE_SLOT(d);
7048ebf2f9SIsaku Yamahata     int rc;
7148ebf2f9SIsaku Yamahata 
729cfaa007SCao jin     pci_bridge_initfn(d, TYPE_PCIE_BUS);
7348ebf2f9SIsaku Yamahata     pcie_port_init_reg(d);
7448ebf2f9SIsaku Yamahata 
7548ebf2f9SIsaku Yamahata     rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
7648ebf2f9SIsaku Yamahata                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
77f8cd1b02SMao Zhongyi                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
78f8cd1b02SMao Zhongyi                   errp);
7948ebf2f9SIsaku Yamahata     if (rc < 0) {
801108b2f8SCao jin         assert(rc == -ENOTSUP);
8109b926d4SIsaku Yamahata         goto err_bridge;
8248ebf2f9SIsaku Yamahata     }
8352ea63deSCao jin 
8448ebf2f9SIsaku Yamahata     rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
85f8cd1b02SMao Zhongyi                                XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
86f8cd1b02SMao Zhongyi                                errp);
8748ebf2f9SIsaku Yamahata     if (rc < 0) {
88a105813aSJonathan Cameron         goto err_msi;
8948ebf2f9SIsaku Yamahata     }
9052ea63deSCao jin 
9148ebf2f9SIsaku Yamahata     rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
92f8cd1b02SMao Zhongyi                        p->port, errp);
9348ebf2f9SIsaku Yamahata     if (rc < 0) {
9409b926d4SIsaku Yamahata         goto err_msi;
9548ebf2f9SIsaku Yamahata     }
960ead87c8SIsaku Yamahata     pcie_cap_flr_init(d);
9748ebf2f9SIsaku Yamahata     pcie_cap_deverr_init(d);
98530a0963SJulia Suvorova     pcie_cap_slot_init(d, s);
9952ea63deSCao jin     pcie_cap_arifwd_init(d);
10052ea63deSCao jin 
10148ebf2f9SIsaku Yamahata     pcie_chassis_create(s->chassis);
10248ebf2f9SIsaku Yamahata     rc = pcie_chassis_add_slot(s);
10348ebf2f9SIsaku Yamahata     if (rc < 0) {
1048b3d2634SEduardo Habkost         error_setg(errp, "Can't add chassis slot, error %d", rc);
10509b926d4SIsaku Yamahata         goto err_pcie_cap;
10648ebf2f9SIsaku Yamahata     }
10752ea63deSCao jin 
108f18c697bSDou Liyang     rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
109f8cd1b02SMao Zhongyi                        PCI_ERR_SIZEOF, errp);
11009b926d4SIsaku Yamahata     if (rc < 0) {
11109b926d4SIsaku Yamahata         goto err;
11209b926d4SIsaku Yamahata     }
11348ebf2f9SIsaku Yamahata 
114f8cd1b02SMao Zhongyi     return;
11509b926d4SIsaku Yamahata 
11609b926d4SIsaku Yamahata err:
11709b926d4SIsaku Yamahata     pcie_chassis_del_slot(s);
11809b926d4SIsaku Yamahata err_pcie_cap:
11909b926d4SIsaku Yamahata     pcie_cap_exit(d);
12009b926d4SIsaku Yamahata err_msi:
12109b926d4SIsaku Yamahata     msi_uninit(d);
12209b926d4SIsaku Yamahata err_bridge:
123f90c2bcdSAlex Williamson     pci_bridge_exitfn(d);
12448ebf2f9SIsaku Yamahata }
12548ebf2f9SIsaku Yamahata 
xio3130_downstream_exitfn(PCIDevice * d)126f90c2bcdSAlex Williamson static void xio3130_downstream_exitfn(PCIDevice *d)
12748ebf2f9SIsaku Yamahata {
128bcb75750SAndreas Färber     PCIESlot *s = PCIE_SLOT(d);
12909b926d4SIsaku Yamahata 
13009b926d4SIsaku Yamahata     pcie_aer_exit(d);
13109b926d4SIsaku Yamahata     pcie_chassis_del_slot(s);
13248ebf2f9SIsaku Yamahata     pcie_cap_exit(d);
13309b926d4SIsaku Yamahata     msi_uninit(d);
134f90c2bcdSAlex Williamson     pci_bridge_exitfn(d);
13548ebf2f9SIsaku Yamahata }
13648ebf2f9SIsaku Yamahata 
137196fd15fSRichard Henderson static const Property xio3130_downstream_props[] = {
138f23b6bdcSMarcel Apfelbaum     DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
139f23b6bdcSMarcel Apfelbaum                     QEMU_PCIE_SLTCAP_PCP_BITNR, true),
140f23b6bdcSMarcel Apfelbaum };
141f23b6bdcSMarcel Apfelbaum 
14248ebf2f9SIsaku Yamahata static const VMStateDescription vmstate_xio3130_downstream = {
14348ebf2f9SIsaku Yamahata     .name = "xio3130-express-downstream-port",
1449d6b9db1SPeter Xu     .priority = MIG_PRI_PCI_BUS,
14548ebf2f9SIsaku Yamahata     .version_id = 1,
14648ebf2f9SIsaku Yamahata     .minimum_version_id = 1,
1476bde6aaaSMichael S. Tsirkin     .post_load = pcie_cap_slot_post_load,
148f026c578SRichard Henderson     .fields = (const VMStateField[]) {
14920daa90aSDr. David Alan Gilbert         VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
150bcb75750SAndreas Färber         VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
151bcb75750SAndreas Färber                        PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
15248ebf2f9SIsaku Yamahata         VMSTATE_END_OF_LIST()
15348ebf2f9SIsaku Yamahata     }
15448ebf2f9SIsaku Yamahata };
15548ebf2f9SIsaku Yamahata 
xio3130_downstream_class_init(ObjectClass * klass,const void * data)15612d1a768SPhilippe Mathieu-Daudé static void xio3130_downstream_class_init(ObjectClass *klass, const void *data)
15740021f08SAnthony Liguori {
15839bffca2SAnthony Liguori     DeviceClass *dc = DEVICE_CLASS(klass);
15940021f08SAnthony Liguori     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
16040021f08SAnthony Liguori 
16140021f08SAnthony Liguori     k->config_write = xio3130_downstream_write_config;
162f8cd1b02SMao Zhongyi     k->realize = xio3130_downstream_realize;
16340021f08SAnthony Liguori     k->exit = xio3130_downstream_exitfn;
16440021f08SAnthony Liguori     k->vendor_id = PCI_VENDOR_ID_TI;
16540021f08SAnthony Liguori     k->device_id = PCI_DEVICE_ID_TI_XIO3130D;
16640021f08SAnthony Liguori     k->revision = XIO3130_REVISION;
167125ee0edSMarcel Apfelbaum     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
16839bffca2SAnthony Liguori     dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
169e3d08143SPeter Maydell     device_class_set_legacy_reset(dc, xio3130_downstream_reset);
17039bffca2SAnthony Liguori     dc->vmsd = &vmstate_xio3130_downstream;
1714f67d30bSMarc-André Lureau     device_class_set_props(dc, xio3130_downstream_props);
17248ebf2f9SIsaku Yamahata }
17340021f08SAnthony Liguori 
1748c43a6f0SAndreas Färber static const TypeInfo xio3130_downstream_info = {
175c41481afSIgor Mammedov     .name          = TYPE_XIO3130_DOWNSTREAM,
176bcb75750SAndreas Färber     .parent        = TYPE_PCIE_SLOT,
17740021f08SAnthony Liguori     .class_init    = xio3130_downstream_class_init,
178*2cd09e47SPhilippe Mathieu-Daudé     .interfaces = (const InterfaceInfo[]) {
17971d78767SEduardo Habkost         { INTERFACE_PCIE_DEVICE },
18071d78767SEduardo Habkost         { }
18171d78767SEduardo Habkost     },
18248ebf2f9SIsaku Yamahata };
18348ebf2f9SIsaku Yamahata 
xio3130_downstream_register_types(void)18483f7d43aSAndreas Färber static void xio3130_downstream_register_types(void)
18548ebf2f9SIsaku Yamahata {
18639bffca2SAnthony Liguori     type_register_static(&xio3130_downstream_info);
18748ebf2f9SIsaku Yamahata }
18848ebf2f9SIsaku Yamahata 
18983f7d43aSAndreas Färber type_init(xio3130_downstream_register_types)
190