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Searched +full:dma +full:- +full:noncoherent (Results 1 – 25 of 31) sorted by relevance

12

/linux-6.15/arch/arc/mm/
Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 #include <linux/dma-map-ops.h>
11 * ARCH specific callbacks for generic noncoherent DMA ops
12 * - hardware IOC not available (or "dma-coherent" not set for device in DT)
13 * - But still handle both coherent and non-coherent requests from caller
15 * For DMA coherent hardware (IOC) generic code suffices
23 * Yeah this bit us - STAR 9000898266 in arch_dma_prep_coherent()
37 * dma-mapping: provide a generic dma-noncoherent implementation)"
40 * |----------------------------------------------------------------
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/linux-6.15/arch/riscv/mm/
Dcache-ops.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <asm/dma-noncoherent.h>
Dpmem.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <asm/dma-noncoherent.h>
DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
3 CFLAGS_init.o := -mcmodel=medany
5 CFLAGS_init.o += -fno-pie
15 obj-y += init.o
16 obj-$(CONFIG_MMU) += extable.o fault.o pageattr.o pgtable.o tlbflush.o
17 obj-y += cacheflush.o
18 obj-y += context.o
19 obj-y += pmem.o
21 obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
22 obj-$(CONFIG_PTDUMP) += ptdump.o
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Ddma-noncoherent.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V specific functions to support DMA for non-coherent devices
8 #include <linux/dma-direct.h>
9 #include <linux/dma-map-ops.h>
12 #include <asm/dma-noncoherent.h>
135 "%s %s: ARCH_DMA_MINALIGN smaller than riscv,cbom-block-size (%d < %d)", in arch_setup_dma_ops()
140 "%s %s: device non-coherent but no non-coherent operations supported", in arch_setup_dma_ops()
143 dev->dma_coherent = coherent; in arch_setup_dma_ops()
149 "Non-coherent DMA support enabled without a block size\n"); in riscv_noncoherent_supported()
/linux-6.15/arch/powerpc/mm/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the linux ppc-specific parts of the memory manager.
6 obj-y := fault.o mem.o pgtable.o maccess.o pageattr.o \
8 pgtable-frag.o ioremap.o ioremap_$(BITS).o \
9 init-common.o mmu_context.o drmem.o \
11 obj-$(CONFIG_PPC_MMU_NOHASH) += nohash/
12 obj-$(CONFIG_PPC_BOOK3S_32) += book3s32/
13 obj-$(CONFIG_PPC_BOOK3S_64) += book3s64/
14 obj-$(CONFIG_NUMA) += numa.o
15 obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
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/linux-6.15/Documentation/devicetree/bindings/dma/
Dsnps,dw-axi-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare AXI DMA Controller
10 - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
13 Synopsys DesignWare AXI DMA Controller DT Binding
16 - $ref: dma-controller.yaml#
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
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/linux-6.15/arch/mips/mm/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the Linux/MIPS-specific parts of the memory manager.
6 obj-y += cache.o
7 obj-y += context.o
8 obj-y += extable.o
9 obj-y += fault.o
10 obj-y += init.o
11 obj-y += mmap.o
12 obj-y += page.o
13 obj-y += page-funcs.o
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/linux-6.15/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
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/linux-6.15/Documentation/devicetree/bindings/net/
Dsophgo,sg2044-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/sophgo,sg2044-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inochi Amaoto <inochiama@gmail.com>
17 - sophgo,sg2044-dwmac
19 - compatible
24 - const: sophgo,sg2044-dwmac
25 - const: snps,dwmac-5.30a
32 - description: GMAC main clock
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/linux-6.15/drivers/cache/
Dstarfive_starlink_cache.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <asm/dma-noncoherent.h>
99 { .compatible = "starfive,jh8100-starlink-cache" },
111 return -ENODEV; in starlink_cache_init()
113 ret = of_property_read_u32(np, "cache-block-size", &block_size); in starlink_cache_init()
118 return -EINVAL; in starlink_cache_init()
122 return -ENOMEM; in starlink_cache_init()
Dax45mp_cache.c1 // SPDX-License-Identifier: GPL-2.0
3 * non-coherent cache functions for Andes AX45MP
10 #include <linux/dma-direction.h>
14 #include <asm/dma-noncoherent.h>
23 /* D-cache operation */
25 #define AX45MP_CCTL_L1D_VA_WB 1 /* Write-back an L1 cache entry */
35 #define AX45MP_CCTL_L2_PA_WB 0x9 /* Write-back an L2 cache entry */
89 /* Write-back L1 and L2 cache entry */
115 start = start & (~(line_size - 1)); in ax45mp_dma_cache_inv()
116 end = ((end + line_size - 1) & (~(line_size - 1))); in ax45mp_dma_cache_inv()
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Dsifive_ccache.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2022 SiFive, Inc.
22 #include <asm/dma-noncoherent.h>
82 return -EINVAL; in ccache_write()
86 return -EINVAL; in ccache_write()
121 { .compatible = "sifive,fu540-c000-ccache" },
122 { .compatible = "sifive,fu740-c000-ccache" },
123 { .compatible = "starfive,jh7100-ccache",
198 if (this_leaf->level == level) in ccache_get_priv_group()
254 struct device *dev = &pdev->dev; in sifive_ccache_probe()
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/linux-6.15/arch/riscv/boot/dts/renesas/
Dr9a07g043f.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <12000000>;
23 #cooling-cells = <2>;
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 mmu-type = "riscv,sv39";
32 i-cache-size = <0x8000>;
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/linux-6.15/arch/riscv/errata/thead/
Derrata.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <asm/dma-noncoherent.h>
20 #include <asm/text-patching.h>
48 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
54 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
60 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
66 * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
84 "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \
136 /* target-c9xx cores report arch_id and impid as 0 */ in errata_probe_pmu()
153 * target-c9xx cores report arch_id and impid as 0 in errata_probe_ghostwrite()
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/linux-6.15/arch/riscv/boot/dts/sophgo/
Dcv18xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <25000000>;
24 d-cache-block-size = <64>;
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/linux-6.15/drivers/of/
Daddress.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/dma-direct.h> /* for bus_dma_region */
58 cp = of_read_number(range + fna, na - fna); in of_bus_default_map()
60 da = of_read_number(addr + fna, na - fna); in of_bus_default_map()
66 return da - cp; in of_bus_default_map()
75 addr[na - 2] = cpu_to_be32(a >> 32); in of_bus_default_translate()
76 addr[na - 1] = cpu_to_be32(a & 0xffffffffu); in of_bus_default_translate()
104 return of_bus_default_translate(addr + 1, offset, na - 1); in of_bus_default_flags_translate()
151 * "vci" is for the /chaos bridge on 1st-gen PCI powermacs in of_bus_pci_match()
190 if (overflows_type(start, r->start)) in __of_address_resource_bounds()
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/linux-6.15/arch/riscv/boot/dts/allwinner/
Dsunxi-d1s-t113.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
4 #include <dt-bindings/clock/sun6i-rtc.h>
5 #include <dt-bindings/clock/sun8i-de2.h>
6 #include <dt-bindings/clock/sun8i-tcon-top.h>
7 #include <dt-bindings/clock/sun20i-d1-ccu.h>
8 #include <dt-bindings/clock/sun20i-d1-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/reset/sun8i-de2.h>
11 #include <dt-bindings/reset/sun20i-d1-ccu.h>
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/linux-6.15/arch/riscv/boot/dts/starfive/
Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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/linux-6.15/arch/riscv/boot/dts/thead/
Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
24 riscv,isa-base = "rv64i";
25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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/linux-6.15/arch/arm64/boot/dts/freescale/
Dimx95.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/dma/fsl-edma.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx95-clock.h"
13 #include "imx95-pinfunc.h"
14 #include "imx95-power.h"
17 interrupt-parent = <&gic>;
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/linux-6.15/drivers/pci/controller/plda/
Dpcie-microchip-host.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
21 #include <linux/pci-ecam.h>
26 #include "pcie-plda.h"
203 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_0, "dma engine 0 error"),
204 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_1, "dma engine 1 error"),
300 struct plda_msi *msi = &port->plda.msi; in mc_pcie_enable_msi()
315 writel_relaxed(lower_32_bits(msi->vector_phy), in mc_pcie_enable_msi()
317 writel_relaxed(upper_32_bits(msi->vector_phy), in mc_pcie_enable_msi()
328 u32 reg = readl_relaxed(port->ctrl_base_addr + PCIE_EVENT_INT); in pcie_events()
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/linux-6.15/drivers/scsi/
D53c700.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
17 /* Turn on for general debugging---too verbose for normal use */
41 #define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1)
81 * for the annoying SCSI-2 requirement for LUN information in
109 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata; in NCR_700_get_sense_cmnd()
111 return hostdata->cmnd; in NCR_700_get_sense_cmnd()
117 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata; in NCR_700_set_depth()
119 hostdata->depth = depth; in NCR_700_set_depth()
124 struct NCR_700_Device_Parameters *hostdata = SDp->hostdata; in NCR_700_get_depth()
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D53c700.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /* NCR (or Symbios) 53c700 and 53c700-66 Driver
6 **-----------------------------------------------------------------------------
9 **-----------------------------------------------------------------------------
20 * The 700-66 can at least do synchronous SCSI up to 10MHz.
27 * minimal wrapper for the purpose---see the NCR_D700 driver for
54 * Bogendoerfer). Added missing SCp->request_bufflen initialisation
73 * Added support for the 53c710 chip (in 53c700 emulation mode only---no
94 * dma cache flushing operations for architectures which need it;
119 #include <asm/dma.h>
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/linux-6.15/arch/arm64/boot/dts/rockchip/
Drk3588-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/power/rk3588-power.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/ata/ahci.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
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