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/qemu/include/hw/sensor/
H A Dtmp105.h4 * Browse the data sheet:
9 * Copyright (C) 2008-2012 Andrzej Zaborowski <balrogg@gmail.com>
12 * later. See the COPYING file in the top-level directory.
27 * temperature. See Table 8 in the data sheet.
H A Demc141x_regs.h4 * Browse the data sheet:
9 * later. See the COPYING file in the top-level directory.
H A Dtmp105_regs.h4 * Browse the data sheet:
9 * Copyright (C) 2008-2012 Andrzej Zaborowski <balrogg@gmail.com>
12 * later. See the COPYING file in the top-level directory.
27 * - adt75
28 * - ds1775
29 * - ds75
30 * - lm75
31 * - lm75a
32 * - max6625
33 * - max6626
[all …]
/qemu/include/hw/misc/
H A Darm_integrator_debug.h4 * Browse the data sheet:
6 …//developer.arm.com/documentation/dui0159/b/peripherals-and-interfaces/debug-leds-and-dip-switch-i…
11 * See the COPYING file in the top-level directory.
/qemu/linux-user/arm/nwfpe/
H A Dfpa11_cprt.c83 fpa11->fType[getFn(opcode)] = typeSingle; in PerformFLT()
84 fpa11->fpreg[getFn(opcode)].fSingle = in PerformFLT()
85 int32_to_float32(readRegister(getRd(opcode)), &fpa11->fp_status); in PerformFLT()
91 fpa11->fType[getFn(opcode)] = typeDouble; in PerformFLT()
92 fpa11->fpreg[getFn(opcode)].fDouble = in PerformFLT()
93 int32_to_float64(readRegister(getRd(opcode)), &fpa11->fp_status); in PerformFLT()
99 fpa11->fType[getFn(opcode)] = typeExtended; in PerformFLT()
100 fpa11->fpreg[getFn(opcode)].fExtended = in PerformFLT()
101 int32_to_floatx80(readRegister(getRd(opcode)), &fpa11->fp_status); in PerformFLT()
119 switch (fpa11->fType[Fn]) in PerformFIX()
[all …]
/qemu/hw/net/
H A Dlance.c2 * QEMU AMD PC-Net II (Am79C970A) emulation
26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
33 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
35 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
44 #include "hw/qdev-properties.h"
53 pcnet_h_reset(&d->state); in parent_lance_reset()
62 pcnet_ioport_writew(&d->state, addr, val & 0xffff); in lance_mem_write()
71 val = pcnet_ioport_readw(&d->state, addr); in lance_mem_read()
107 PCNetState *s = &d->state; in lance_realize()
109 memory_region_init_io(&s->mmio, OBJECT(d), &lance_mem_ops, d, in lance_realize()
[all …]
H A Dpcnet-pci.c2 * QEMU AMD PC-Net II (Am79C970A) PCI emulation
26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
33 #include "hw/qdev-properties.h"
72 s->prom[addr & 15] = val; in pcnet_aprom_writeb()
79 uint32_t val = s->prom[addr & 15]; in pcnet_aprom_readb()
110 return ((uint64_t)1 << (size * 8)) - 1; in pcnet_ioport_read()
114 uint64_t data, unsigned size) in pcnet_ioport_write() argument
118 trace_pcnet_ioport_write(opaque, addr, data, size); in pcnet_ioport_write()
121 pcnet_aprom_writeb(d, addr, data); in pcnet_ioport_write()
123 pcnet_aprom_writeb(d, addr, data & 0xff); in pcnet_ioport_write()
[all …]
H A Dsmc91c111.c17 #include "hw/qdev-properties.h"
27 * Maximum size of a data frame, including the leading status word
28 * and byte count fields and the trailing CRC, last data byte
29 * and control byte (per figure 8-1 in the Microchip Technology
62 uint8_t data[NUM_PACKETS][MAX_PACKET_SIZE]; member
90 VMSTATE_BUFFER_UNSAFE(data, smc91c111_state, 0,
147 if (s->tx_fifo_len == 0) in smc91c111_update()
148 s->int_level |= INT_TX_EMPTY; in smc91c111_update()
149 if (s->tx_fifo_done_len != 0) in smc91c111_update()
150 s->int_level |= INT_TX; in smc91c111_update()
[all …]
H A Dpcnet.c2 * QEMU AMD PC-Net II (Am79C970A) emulation
26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
33 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
35 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
41 #include "hw/qdev-properties.h"
65 #define CSR_INIT(S) !!(((S)->csr[0])&0x0001)
66 #define CSR_STRT(S) !!(((S)->csr[0])&0x0002)
67 #define CSR_STOP(S) !!(((S)->csr[0])&0x0004)
68 #define CSR_TDMD(S) !!(((S)->csr[0])&0x0008)
69 #define CSR_TXON(S) !!(((S)->csr[0])&0x0010)
[all …]
/qemu/hw/ide/
H A Dich.c21 * lspci dump of a ICH-9 real device
23 …2801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0])
25 …* Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- Fast…
26 …* Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR…
34 * Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K]
35 * Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+
36 * Address: fee0f00c Data: 41d9
38 * Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
39 * Status: D0 PME-Enable- DSel=0 DScale=0 PME-
71 #include "hw/ide/ahci-pci.h"
[all …]
H A Dsii3112.c7 * See the COPYING file in the top-level directory.
20 #include "ide-internal.h"
39 * Internal Register Space - BAR5 (section 6.7 of the data sheet).
50 val = d->i.bmdma[0].cmd; in sii3112_reg_read()
53 val = d->regs[0].swdata; in sii3112_reg_read()
56 val = d->i.bmdma[0].status; in sii3112_reg_read()
62 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[0], addr - 4, size); in sii3112_reg_read()
65 val = d->i.bmdma[1].cmd; in sii3112_reg_read()
68 val = d->regs[1].swdata; in sii3112_reg_read()
71 val = d->i.bmdma[1].status; in sii3112_reg_read()
[all …]
/qemu/hw/fsi/
H A Daspeed_apb2opb.c2 * SPDX-License-Identifier: GPL-2.0-or-later
5 * ASPEED APB-OPB FSI interface
6 * IBM On-chip Peripheral Bus
16 #include "hw/qdev-core.h"
66 * The following magic values came from AST2600 data sheet
83 memory_region_set_address(&fsi->iomem, addr); in fsi_opb_fsi_master_address()
90 memory_region_set_address(&fsi->opb2fsi, addr); in fsi_opb_opb2fsi_address()
109 return s->regs[reg]; in fsi_aspeed_apb2opb_read()
113 MemTxAttrs attrs, uint32_t *data, in fsi_aspeed_apb2opb_rw() argument
121 address_space_stl_le(as, addr, *data, attrs, &res); in fsi_aspeed_apb2opb_rw()
[all …]
/qemu/hw/pci-host/
H A Di440fx.c31 #include "hw/pci-host/i440fx.h"
32 #include "hw/qdev-properties.h"
37 #include "qemu/error-report.h"
41 * I440FX chipset data sheet.
77 dev->config[I440FX_SMRAM] = 0x02; in i440fx_realize()
90 for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) { in i440fx_update_memory_mappings()
91 pam_update(&d->pam_regions[i], i, in i440fx_update_memory_mappings()
92 pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]); in i440fx_update_memory_mappings()
94 memory_region_set_enabled(&d->smram_region, in i440fx_update_memory_mappings()
95 !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN)); in i440fx_update_memory_mappings()
[all …]
/qemu/hw/misc/
H A Dnpcm_clk.c21 #include "hw/qdev-clock.h"
23 #include "qemu/error-report.h"
38 #define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex-A9 Cores */
129 * These reset values were taken from version 0.91 of the NPCM750R data sheet.
131 * All are loaded on power-up reset. CLKENx and SWRSTR should also be loaded on
157 * These reset values were taken from version 0.92 of the NPCM8xx data sheet.
201 #define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
204 #define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
207 #define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
214 uint32_t con = s->clk->regs[s->reg]; in npcm7xx_clk_update_pll()
[all …]
/qemu/hw/nvram/
H A Dnrf51_nvm.c2 * Nordic Semiconductor nRF51 non-volatile memory
9 * See nRF51 reference manual and product sheet sections:
10 * + Non-Volatile Memory Controller (NVMC)
14 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
17 * the COPYING file in the top-level directory.
26 #include "hw/qdev-properties.h"
175 assert(offset < sizeof(s->uicr_content)); in uicr_read()
176 return s->uicr_content[offset / 4]; in uicr_read()
184 assert(offset < sizeof(s->uicr_content)); in uicr_write()
185 s->uicr_content[offset / 4] = value; in uicr_write()
[all …]
/qemu/hw/sensor/
H A Dlsm303dlhc_mag.c9 * SPDX-License-Identifier: GPL-2.0-or-later
13 * The I2C address associated with this device is set on the command-line when
16 * Get and set functions for 'mag-x', 'mag-y' and 'mag-z' assume that
78 * in units "lsb per Gauss" (see data sheet table 3). There is no documented
89 int gm = extract32(s->crb, 5, 3); in lsm303dlhc_mag_get_x()
92 int64_t value = muldiv64(s->x, 100000, xy_gain[gm]); in lsm303dlhc_mag_get_x()
100 int gm = extract32(s->crb, 5, 3); in lsm303dlhc_mag_get_y()
103 int64_t value = muldiv64(s->y, 100000, xy_gain[gm]); in lsm303dlhc_mag_get_y()
111 int gm = extract32(s->crb, 5, 3); in lsm303dlhc_mag_get_z()
114 int64_t value = muldiv64(s->z, 100000, z_gain[gm]); in lsm303dlhc_mag_get_z()
[all …]
H A Dmax31785.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Maxim MAX31785 PMBus 6-Channel Fan Controller
42 /* defaults as per the data sheet */
140 * |23-254 | Reserved |
172 switch (pmdev->code) { in max31785_read_byte()
175 if (pmdev->page <= MAX31785_MAX_FAN_PAGE) { in max31785_read_byte()
176 pmbus_send8(pmdev, pmdev->pages[pmdev->page].fan_config_1_2); in max31785_read_byte()
181 if (pmdev->page <= MAX31785_MAX_FAN_PAGE) { in max31785_read_byte()
182 pmbus_send16(pmdev, pmdev->pages[pmdev->page].fan_command_1); in max31785_read_byte()
187 if (pmdev->page <= MAX31785_MAX_FAN_PAGE) { in max31785_read_byte()
[all …]
/qemu/hw/gpio/
H A Dpl061.c16 * + QOM property "pullups": an integer defining whether non-floating lines
19 * This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should
22 * + QOM property "pulldowns": an integer defining whether non-floating lines
25 * This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should
35 #include "hw/qdev-properties.h"
58 uint32_t data; member
81 /* Properties, for non-Luminary PL061 */
92 VMSTATE_UINT32(data, PL061State),
124 if (s->id == pl061_id_luminary) { in pl061_floating()
129 floating = ~(s->pur | s->pdr); in pl061_floating()
[all …]
/qemu/hw/arm/
H A Dstellaris.c13 #include "hw/core/split-irq.h"
23 #include "system/address-spaces.h"
29 #include "hw/watchdog/cmsdk-apb-watchdog.h"
32 #include "hw/timer/stellaris-gptm.h"
33 #include "hw/qdev-clock.h"
59 * See Stellaris Data Sheet chapter 5.2.5 "System Control",
76 #define DEV_CAP(_dc, _cap) extract32(board->dc##_dc, DC##_dc##_##_cap, 1)
92 #define TYPE_STELLARIS_SYS "stellaris-sys"
113 /* Properties (all read-only registers) */
127 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()
[all …]
/qemu/hw/rtc/
H A Dmc146818rtc.c4 * Copyright (c) 2003-2004 Fabrice Bellard
32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-properties-system.h"
44 #include "qapi/qapi-events-misc.h"
82 return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) && in rtc_running()
83 (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20); in rtc_running()
90 return s->base_rtc * NANOSECONDS_PER_SECOND + in get_guest_rtc_ns()
91 guest_clock - s->last_update + s->offset; in get_guest_rtc_ns()
96 if (s->irq_coalesced == 0) { in rtc_coalesced_timer_update()
97 timer_del(s->coalesced_timer); in rtc_coalesced_timer_update()
[all …]