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/linux-5.10/Documentation/devicetree/bindings/serial/
Dsnps-dw-apb-uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/serial.yaml#
18 - items:
19 - enum:
20 - renesas,r9a06g032-uart
21 - renesas,r9a06g033-uart
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Dcdns,uart.txt4 - compatible :
5 Use "xlnx,xuartps","cdns,uart-r1p8" for Zynq-7xxx SoC.
6 Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
7 - reg: Should contain UART controller registers location and length.
8 - interrupts: Should contain UART controller interrupts.
9 - clocks: Must contain phandles to the UART clocks
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Tuple to identify input clocks, must contain "uart_clk" and "pclk"
12 See ../clocks/clock-bindings.txt for details.
16 - cts-override : Override the CTS modem status signal. This signal will
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/linux-5.10/drivers/hwtracing/intel_th/
Dgth.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2014-2015 Intel Corporation.
42 REG_GTH_SCR = 0xc8, /* Source control (storeEn override) */
45 REG_GTH_DESTOVR = 0xdc, /* Destination override */
53 /* Common Capture Sequencer (CTS) registers */
66 /* waiting for Trigger status to assert for CTS */
/linux-5.10/drivers/net/wireless/ath/ath5k/
Ddesc.h2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
24 * struct ath5k_hw_rx_ctl - Common hardware RX control descriptor
38 * struct ath5k_hw_rx_status - Common hardware RX status descriptor
105 * enum ath5k_phy_error_code - PHY Error codes
113 * @AR5K_RX_PHY_ERROR_TOR: Transmit override receive
151 * struct ath5k_hw_2w_tx_ctl - 5210/5211 hardware 2-word TX control descriptor
166 #define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 /* RTS/CTS enable */
168 #define AR5K_2W_TX_DESC_CTL0_VEOL_5211 0x00800000 /* [5211] virtual end-of-list */
173 (ah->ah_version == AR5K_AR5210 ? \
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/linux-5.10/drivers/tty/serial/8250/
D8250_dw.c1 // SPDX-License-Identifier: GPL-2.0+
73 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_modify_msr()
75 /* Override any modem control signals if needed */ in dw8250_modify_msr()
77 value |= d->msr_mask_on; in dw8250_modify_msr()
78 value &= ~d->msr_mask_off; in dw8250_modify_msr()
89 (void)p->serial_in(p, UART_RX); in dw8250_force_idle()
94 void __iomem *offset = p->membase + (UART_LCR << p->regshift); in dw8250_check_lcr()
98 while (tries--) { in dw8250_check_lcr()
99 unsigned int lcr = p->serial_in(p, UART_LCR); in dw8250_check_lcr()
107 if (p->type == PORT_OCTEON) in dw8250_check_lcr()
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/linux-5.10/drivers/gpu/drm/omapdrm/dss/
Dhdmi4_core.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
32 return core->base + HDMI_CORE_AV; in hdmi_av_base()
37 void __iomem *base = core->base; in hdmi4_core_ddc_init()
50 return -ETIMEDOUT; in hdmi4_core_ddc_init()
61 return -ETIMEDOUT; in hdmi4_core_ddc_init()
71 return -ETIMEDOUT; in hdmi4_core_ddc_init()
80 void __iomem *base = core->base; in hdmi4_core_ddc_read()
87 return -ETIMEDOUT; in hdmi4_core_ddc_read()
112 return -EIO; in hdmi4_core_ddc_read()
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/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi4_core.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
33 return core->base + HDMI_CORE_AV; in hdmi_av_base()
38 void __iomem *base = core->base; in hdmi_core_ddc_init()
51 return -ETIMEDOUT; in hdmi_core_ddc_init()
62 return -ETIMEDOUT; in hdmi_core_ddc_init()
72 return -ETIMEDOUT; in hdmi_core_ddc_init()
81 void __iomem *base = core->base; in hdmi_core_ddc_edid()
90 return -ETIMEDOUT; in hdmi_core_ddc_edid()
118 return -EIO; in hdmi_core_ddc_edid()
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/linux-5.10/drivers/net/wireless/ath/ath6kl/
Dtarget.h2 * Copyright (c) 2004-2010 Atheros Communications Inc.
161 * Pointer to application-defined area, if any.
175 * General-purpose flag bits, similar to ATH6KL_OPTION_* flags.
189 /* Override Target application start address */
225 u32 hi_num_bpatch_streams; /* 0x70 -- unused */
235 * NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts
251 * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
273 * 0xbc - [31:0]: idle timeout in ms
281 /* If non-zero, override values sent to Host in WMI_READY event. */
286 * Percentage of high priority RX traffic to total expected RX traffic -
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/linux-5.10/drivers/tty/serial/
Daltera_uart.c1 // SPDX-License-Identifier: GPL-2.0+
3 * altera_uart.c -- Altera UART driver
5 * Based on mcf.c -- Freescale ColdFire UART driver
7 * (C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
54 #define ALTERA_UART_STATUS_DCTS_MSK 0x0400 /* CTS logic-level change */
55 #define ALTERA_UART_STATUS_CTS_MSK 0x0800 /* CTS logic state */
70 #define ALTERA_UART_CONTROL_DCTS_MSK 0x0400 /* Interrupt on CTS change */
75 * Local per-uart structure.
86 return readl(port->membase + (reg << port->regshift)); in altera_uart_readl()
91 writel(dat, port->membase + (reg << port->regshift)); in altera_uart_writel()
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Dmux.c1 // SPDX-License-Identifier: GPL-2.0+
4 ** serial driver for the Mux console found in some PA-RISC servers.
7 ** (c) Copyright 2002 Hewlett-Packard Company
26 #include <asm/parisc-device.h>
63 #define UART_PUT_CHAR(p, c) __raw_writel((c), (p)->membase + IO_DATA_REG_OFFSET)
64 #define UART_GET_FIFO_CNT(p) __raw_readl((p)->membase + IO_DCOUNT_REG_OFFSET)
67 * get_mux_port_count - Get the number of available ports on the Mux.
73 * are connected. This function can override the IODC and
82 /* If this is the built-in Mux for the K-Class (Eole CAP/MUX), in get_mux_port_count()
86 if(dev->id.hversion == 0x15) in get_mux_port_count()
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Dsirfsoc_uart.c1 // SPDX-License-Identifier: GPL-2.0+
24 #include <linux/dma-direction.h>
25 #include <linux/dma-mapping.h>
70 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_tx_empty()
71 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; in sirfsoc_uart_tx_empty()
72 reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status); in sirfsoc_uart_tx_empty()
73 return (reg & ufifo_st->ff_empty(port)) ? TIOCSER_TEMT : 0; in sirfsoc_uart_tx_empty()
79 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_get_mctrl()
80 if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled) in sirfsoc_uart_get_mctrl()
82 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { in sirfsoc_uart_get_mctrl()
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/linux-5.10/fs/crypto/
Dkeysetup.c1 // SPDX-License-Identifier: GPL-2.0
19 .friendly_name = "AES-256-XTS",
26 .friendly_name = "AES-256-CTS-CBC",
27 .cipher_str = "cts(cbc(aes))",
32 .friendly_name = "AES-128-CBC-ESSIV",
39 .friendly_name = "AES-128-CTS-CBC",
40 .cipher_str = "cts(cbc(aes))",
59 if (S_ISREG(inode->i_mode)) in select_encryption_mode()
62 if (S_ISDIR(inode->i_mode) || S_ISLNK(inode->i_mode)) in select_encryption_mode()
66 inode->i_ino, (inode->i_mode & S_IFMT)); in select_encryption_mode()
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/linux-5.10/drivers/usb/serial/
Dark3116.c1 // SPDX-License-Identifier: GPL-2.0+
9 * - implements a driver for the arkmicro ark3116 chipset (vendor=0x6547,
10 * productid=0x0232) (used in a datacable called KQ-U8A)
52 struct usb_device *dev = serial->dev; in is_irda()
53 if (le16_to_cpu(dev->descriptor.idVendor) == 0x18ec && in is_irda()
54 le16_to_cpu(dev->descriptor.idProduct) == 0x3118) in is_irda()
82 result = usb_control_msg(serial->dev, in ark3116_write_reg()
83 usb_sndctrlpipe(serial->dev, 0), in ark3116_write_reg()
97 result = usb_control_msg(serial->dev, in ark3116_read_reg()
98 usb_rcvctrlpipe(serial->dev, 0), in ark3116_read_reg()
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/linux-5.10/drivers/net/wireless/intel/iwlwifi/fw/api/
Dtx.h8 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
9 * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
30 * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation
65 * enum iwl_tx_flags - bitmasks for tx_flags in TX command
66 * @TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
80 * @TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control.
81 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
82 * @TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
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/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dmain.c3 * Copyright (c) 2013 Hauke Mehrtens <hauke@hauke-m.de>
50 /* n-mode support capability */
82 #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
133 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
167 #define BRCMS_PLCP_AUTO -1
172 #define BRCMS_PROTECTION_AUTO -1
199 /* MSC in use,indicates b0-6 holds an mcs */
207 /* bit indicate to override mcs only */
361 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK] in brcms_basic_rate()
363 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK]; in brcms_basic_rate()
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/linux-5.10/arch/arm/boot/dts/
Darmada-370.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
15 #include "armada-370-xp.dtsi"
18 #address-cells = <1>;
19 #size-cells = <1>;
22 compatible = "marvell,armada370", "marvell,armada-370-xp";
31 compatible = "marvell,armada370-mbus", "simple-bus";
39 compatible = "marvell,armada-370-pcie";
43 #address-cells = <3>;
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Dmeson8.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
19 #address-cells = <1>;
20 #size-cells = <0>;
24 compatible = "arm,cortex-a9";
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Dmeson8b.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-a5";
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/linux-5.10/drivers/gpu/drm/bridge/synopsys/
Ddw-hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
19 #include <linux/dma-mapping.h>
22 #include <media/cec-notifier.h>
24 #include <uapi/linux/media-bus-format.h>
37 #include "dw-hdmi-audio.h"
38 #include "dw-hdmi-cec.h"
39 #include "dw-hdmi.h"
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/linux-5.10/drivers/gpu/drm/bridge/
Dsii9234.c1 // SPDX-License-Identifier: GPL-2.0-or-later
198 struct i2c_client *client = ctx->client[id]; in sii9234_writeb()
200 if (ctx->i2c_error) in sii9234_writeb()
201 return ctx->i2c_error; in sii9234_writeb()
205 dev_err(ctx->dev, "writeb: %4s[0x%02x] <- 0x%02x\n", in sii9234_writeb()
207 ctx->i2c_error = ret; in sii9234_writeb()
216 struct i2c_client *client = ctx->client[id]; in sii9234_writebm()
218 if (ctx->i2c_error) in sii9234_writebm()
219 return ctx->i2c_error; in sii9234_writebm()
223 dev_err(ctx->dev, "writebm: %4s[0x%02x] <- 0x%02x\n", in sii9234_writebm()
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/linux-5.10/drivers/tty/
Drocket_int.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * rocket_int.h --- internal header file for rocket.c
34 * byte-swapping the I/O instructions. However, all accesses using
35 * sOutDW aren't really 32-bit accesses, but should be handled in byte
36 * order. Hence the use of the cpu_to_le32() macro to byte-swap
37 * things to no-op the byte swapping done by the big-endian outl()
93 #define CTLID_NULL -1 /* no controller exists */
97 #define AIOPID_NULL -1 /* no AIOP or channel exists */
101 Global Register Offsets - Direct Access - Fixed values
112 Channel Register Offsets for 1st channel in AIOP - Direct Access
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/linux-5.10/drivers/net/wireless/ralink/rt2x00/
Drt2x00queue.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
5 Copyright (C) 2004 - 2009 Gertjan van Wingerde <gwingerde@gmail.com>
18 #include <linux/dma-mapping.h>
25 struct data_queue *queue = entry->queue; in rt2x00queue_alloc_rxskb()
26 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt2x00queue_alloc_rxskb()
37 frame_size = queue->data_size + queue->desc_size + queue->winfo_size; in rt2x00queue_alloc_rxskb()
40 * The payload should be aligned to a 4-byte boundary, in rt2x00queue_alloc_rxskb()
79 skb_dma = dma_map_single(rt2x00dev->dev, skb->data, skb->len, in rt2x00queue_alloc_rxskb()
81 if (unlikely(dma_mapping_error(rt2x00dev->dev, skb_dma))) { in rt2x00queue_alloc_rxskb()
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/linux-5.10/drivers/char/pcmcia/
Dsynclink_cs.c83 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
85 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
197 int if_mode; /* serial interface selection (RS-232, v.35 etc) */
295 #define IRQ_CTS BIT10 // CTS status change
309 #define CTS BIT1 // CTS state macro
321 #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
322 #define read_reg(info, reg) inb((info)->io_base + (reg))
324 #define read_reg16(info, reg) inw((info)->io_base + (reg))
325 #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
339 info->imra_value |= mask; in irq_disable()
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/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_aux.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
36 aux110->base.ctx
38 (aux110->regs->reg_name)
41 engine->ctx->logger
47 aux110->shift->field_name, aux110->mask->field_name
77 dal_ddc_close(engine->ddc); in release_engine()
79 engine->ddc = NULL; in release_engine()
185 ((request->type == AUX_TRANSACTION_TYPE_DP) && in submit_channel_request()
186 (request->action == I2CAUX_TRANSACTION_ACTION_DP_WRITE)) || in submit_channel_request()
187 ((request->type == AUX_TRANSACTION_TYPE_I2C) && in submit_channel_request()
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/linux-5.10/drivers/net/wireless/ath/ath10k/
Dwmi.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
28 * 1. Add new WMI commands ONLY within the specified range - 0x9000 - 0x9fff
44 * variable is already 4-byte aligned by virtue of being a u32
526 * for wmi_services is 64 as target is using only 4-bits of each 32-bit
532 __le32_to_cpu((wmi_svc_bmap)[((svc_id) - (len)) / 28]) & \
533 BIT(((((svc_id) - (len)) % 28) & 0x1f) + 4))
1159 /** DFS-specific commands */
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