Lines Matching +full:cts +full:- +full:override
1 // SPDX-License-Identifier: GPL-2.0+
24 #include <linux/dma-direction.h>
25 #include <linux/dma-mapping.h>
70 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_tx_empty()
71 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; in sirfsoc_uart_tx_empty()
72 reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status); in sirfsoc_uart_tx_empty()
73 return (reg & ufifo_st->ff_empty(port)) ? TIOCSER_TEMT : 0; in sirfsoc_uart_tx_empty()
79 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_get_mctrl()
80 if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled) in sirfsoc_uart_get_mctrl()
82 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { in sirfsoc_uart_get_mctrl()
83 if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) & in sirfsoc_uart_get_mctrl()
89 if (!gpio_get_value(sirfport->cts_gpio)) in sirfsoc_uart_get_mctrl()
103 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_set_mctrl()
109 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) in sirfsoc_uart_set_mctrl()
110 wr_regl(port, ureg->sirfsoc_line_ctrl, in sirfsoc_uart_set_mctrl()
111 rd_regl(port, ureg->sirfsoc_line_ctrl) | in sirfsoc_uart_set_mctrl()
114 wr_regl(port, ureg->sirfsoc_mode1, in sirfsoc_uart_set_mctrl()
115 rd_regl(port, ureg->sirfsoc_mode1) | in sirfsoc_uart_set_mctrl()
118 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) in sirfsoc_uart_set_mctrl()
119 wr_regl(port, ureg->sirfsoc_line_ctrl, in sirfsoc_uart_set_mctrl()
120 rd_regl(port, ureg->sirfsoc_line_ctrl) & in sirfsoc_uart_set_mctrl()
123 wr_regl(port, ureg->sirfsoc_mode1, in sirfsoc_uart_set_mctrl()
124 rd_regl(port, ureg->sirfsoc_mode1) & in sirfsoc_uart_set_mctrl()
128 if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled) in sirfsoc_uart_set_mctrl()
130 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { in sirfsoc_uart_set_mctrl()
131 current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF; in sirfsoc_uart_set_mctrl()
133 wr_regl(port, ureg->sirfsoc_afc_ctrl, val); in sirfsoc_uart_set_mctrl()
136 gpio_set_value(sirfport->rts_gpio, 1); in sirfsoc_uart_set_mctrl()
138 gpio_set_value(sirfport->rts_gpio, 0); in sirfsoc_uart_set_mctrl()
145 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_stop_tx()
146 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; in sirfsoc_uart_stop_tx()
148 if (sirfport->tx_dma_chan) { in sirfsoc_uart_stop_tx()
149 if (sirfport->tx_dma_state == TX_DMA_RUNNING) { in sirfsoc_uart_stop_tx()
150 dmaengine_pause(sirfport->tx_dma_chan); in sirfsoc_uart_stop_tx()
151 sirfport->tx_dma_state = TX_DMA_PAUSE; in sirfsoc_uart_stop_tx()
153 if (!sirfport->is_atlas7) in sirfsoc_uart_stop_tx()
154 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_stop_tx()
155 rd_regl(port, ureg->sirfsoc_int_en_reg) & in sirfsoc_uart_stop_tx()
156 ~uint_en->sirfsoc_txfifo_empty_en); in sirfsoc_uart_stop_tx()
158 wr_regl(port, ureg->sirfsoc_int_en_clr_reg, in sirfsoc_uart_stop_tx()
159 uint_en->sirfsoc_txfifo_empty_en); in sirfsoc_uart_stop_tx()
162 if (sirfport->uart_reg->uart_type == SIRF_USP_UART) in sirfsoc_uart_stop_tx()
163 wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port, in sirfsoc_uart_stop_tx()
164 ureg->sirfsoc_tx_rx_en) & ~SIRFUART_TX_EN); in sirfsoc_uart_stop_tx()
165 if (!sirfport->is_atlas7) in sirfsoc_uart_stop_tx()
166 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_stop_tx()
167 rd_regl(port, ureg->sirfsoc_int_en_reg) & in sirfsoc_uart_stop_tx()
168 ~uint_en->sirfsoc_txfifo_empty_en); in sirfsoc_uart_stop_tx()
170 wr_regl(port, ureg->sirfsoc_int_en_clr_reg, in sirfsoc_uart_stop_tx()
171 uint_en->sirfsoc_txfifo_empty_en); in sirfsoc_uart_stop_tx()
177 struct uart_port *port = &sirfport->port; in sirfsoc_uart_tx_with_dma()
178 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_tx_with_dma()
179 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; in sirfsoc_uart_tx_with_dma()
180 struct circ_buf *xmit = &port->state->xmit; in sirfsoc_uart_tx_with_dma()
185 tran_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); in sirfsoc_uart_tx_with_dma()
186 tran_start = (unsigned long)(xmit->buf + xmit->tail); in sirfsoc_uart_tx_with_dma()
190 if (sirfport->tx_dma_state == TX_DMA_PAUSE) { in sirfsoc_uart_tx_with_dma()
191 dmaengine_resume(sirfport->tx_dma_chan); in sirfsoc_uart_tx_with_dma()
194 if (sirfport->tx_dma_state == TX_DMA_RUNNING) in sirfsoc_uart_tx_with_dma()
196 if (!sirfport->is_atlas7) in sirfsoc_uart_tx_with_dma()
197 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_tx_with_dma()
198 rd_regl(port, ureg->sirfsoc_int_en_reg)& in sirfsoc_uart_tx_with_dma()
199 ~(uint_en->sirfsoc_txfifo_empty_en)); in sirfsoc_uart_tx_with_dma()
201 wr_regl(port, ureg->sirfsoc_int_en_clr_reg, in sirfsoc_uart_tx_with_dma()
202 uint_en->sirfsoc_txfifo_empty_en); in sirfsoc_uart_tx_with_dma()
212 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP); in sirfsoc_uart_tx_with_dma()
213 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, in sirfsoc_uart_tx_with_dma()
214 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)| in sirfsoc_uart_tx_with_dma()
219 tran_size -= pio_tx_size; in sirfsoc_uart_tx_with_dma()
223 if (!sirfport->is_atlas7) in sirfsoc_uart_tx_with_dma()
224 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_tx_with_dma()
225 rd_regl(port, ureg->sirfsoc_int_en_reg)| in sirfsoc_uart_tx_with_dma()
226 uint_en->sirfsoc_txfifo_empty_en); in sirfsoc_uart_tx_with_dma()
228 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_tx_with_dma()
229 uint_en->sirfsoc_txfifo_empty_en); in sirfsoc_uart_tx_with_dma()
230 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START); in sirfsoc_uart_tx_with_dma()
233 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP); in sirfsoc_uart_tx_with_dma()
234 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, in sirfsoc_uart_tx_with_dma()
235 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)& in sirfsoc_uart_tx_with_dma()
237 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START); in sirfsoc_uart_tx_with_dma()
240 sirfport->tx_dma_addr = dma_map_single(port->dev, in sirfsoc_uart_tx_with_dma()
241 xmit->buf + xmit->tail, in sirfsoc_uart_tx_with_dma()
243 sirfport->tx_dma_desc = dmaengine_prep_slave_single( in sirfsoc_uart_tx_with_dma()
244 sirfport->tx_dma_chan, sirfport->tx_dma_addr, in sirfsoc_uart_tx_with_dma()
246 if (!sirfport->tx_dma_desc) { in sirfsoc_uart_tx_with_dma()
247 dev_err(port->dev, "DMA prep slave single fail\n"); in sirfsoc_uart_tx_with_dma()
250 sirfport->tx_dma_desc->callback = in sirfsoc_uart_tx_with_dma()
252 sirfport->tx_dma_desc->callback_param = (void *)sirfport; in sirfsoc_uart_tx_with_dma()
253 sirfport->transfer_size = tran_size; in sirfsoc_uart_tx_with_dma()
255 dmaengine_submit(sirfport->tx_dma_desc); in sirfsoc_uart_tx_with_dma()
256 dma_async_issue_pending(sirfport->tx_dma_chan); in sirfsoc_uart_tx_with_dma()
257 sirfport->tx_dma_state = TX_DMA_RUNNING; in sirfsoc_uart_tx_with_dma()
264 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_start_tx()
265 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; in sirfsoc_uart_start_tx()
266 if (sirfport->tx_dma_chan) in sirfsoc_uart_start_tx()
269 if (sirfport->uart_reg->uart_type == SIRF_USP_UART) in sirfsoc_uart_start_tx()
270 wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port, in sirfsoc_uart_start_tx()
271 ureg->sirfsoc_tx_rx_en) | SIRFUART_TX_EN); in sirfsoc_uart_start_tx()
272 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP); in sirfsoc_uart_start_tx()
273 sirfsoc_uart_pio_tx_chars(sirfport, port->fifosize); in sirfsoc_uart_start_tx()
274 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START); in sirfsoc_uart_start_tx()
275 if (!sirfport->is_atlas7) in sirfsoc_uart_start_tx()
276 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_start_tx()
277 rd_regl(port, ureg->sirfsoc_int_en_reg)| in sirfsoc_uart_start_tx()
278 uint_en->sirfsoc_txfifo_empty_en); in sirfsoc_uart_start_tx()
280 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_start_tx()
281 uint_en->sirfsoc_txfifo_empty_en); in sirfsoc_uart_start_tx()
288 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_stop_rx()
289 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; in sirfsoc_uart_stop_rx()
291 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0); in sirfsoc_uart_stop_rx()
292 if (sirfport->rx_dma_chan) { in sirfsoc_uart_stop_rx()
293 if (!sirfport->is_atlas7) in sirfsoc_uart_stop_rx()
294 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_stop_rx()
295 rd_regl(port, ureg->sirfsoc_int_en_reg) & in sirfsoc_uart_stop_rx()
297 sirfport->uart_reg->uart_type) | in sirfsoc_uart_stop_rx()
298 uint_en->sirfsoc_rx_done_en)); in sirfsoc_uart_stop_rx()
300 wr_regl(port, ureg->sirfsoc_int_en_clr_reg, in sirfsoc_uart_stop_rx()
302 sirfport->uart_reg->uart_type)| in sirfsoc_uart_stop_rx()
303 uint_en->sirfsoc_rx_done_en); in sirfsoc_uart_stop_rx()
304 dmaengine_terminate_all(sirfport->rx_dma_chan); in sirfsoc_uart_stop_rx()
306 if (!sirfport->is_atlas7) in sirfsoc_uart_stop_rx()
307 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_stop_rx()
308 rd_regl(port, ureg->sirfsoc_int_en_reg)& in sirfsoc_uart_stop_rx()
310 sirfport->uart_reg->uart_type))); in sirfsoc_uart_stop_rx()
312 wr_regl(port, ureg->sirfsoc_int_en_clr_reg, in sirfsoc_uart_stop_rx()
314 sirfport->uart_reg->uart_type)); in sirfsoc_uart_stop_rx()
321 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_disable_ms()
322 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; in sirfsoc_uart_disable_ms()
324 if (!sirfport->hw_flow_ctrl) in sirfsoc_uart_disable_ms()
326 sirfport->ms_enabled = false; in sirfsoc_uart_disable_ms()
327 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { in sirfsoc_uart_disable_ms()
328 wr_regl(port, ureg->sirfsoc_afc_ctrl, in sirfsoc_uart_disable_ms()
329 rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3FF); in sirfsoc_uart_disable_ms()
330 if (!sirfport->is_atlas7) in sirfsoc_uart_disable_ms()
331 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_disable_ms()
332 rd_regl(port, ureg->sirfsoc_int_en_reg)& in sirfsoc_uart_disable_ms()
333 ~uint_en->sirfsoc_cts_en); in sirfsoc_uart_disable_ms()
335 wr_regl(port, ureg->sirfsoc_int_en_clr_reg, in sirfsoc_uart_disable_ms()
336 uint_en->sirfsoc_cts_en); in sirfsoc_uart_disable_ms()
338 disable_irq(gpio_to_irq(sirfport->cts_gpio)); in sirfsoc_uart_disable_ms()
344 struct uart_port *port = &sirfport->port; in sirfsoc_uart_usp_cts_handler()
345 spin_lock(&port->lock); in sirfsoc_uart_usp_cts_handler()
346 if (gpio_is_valid(sirfport->cts_gpio) && sirfport->ms_enabled) in sirfsoc_uart_usp_cts_handler()
348 !gpio_get_value(sirfport->cts_gpio)); in sirfsoc_uart_usp_cts_handler()
349 spin_unlock(&port->lock); in sirfsoc_uart_usp_cts_handler()
356 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_enable_ms()
357 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; in sirfsoc_uart_enable_ms()
359 if (!sirfport->hw_flow_ctrl) in sirfsoc_uart_enable_ms()
361 sirfport->ms_enabled = true; in sirfsoc_uart_enable_ms()
362 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { in sirfsoc_uart_enable_ms()
363 wr_regl(port, ureg->sirfsoc_afc_ctrl, in sirfsoc_uart_enable_ms()
364 rd_regl(port, ureg->sirfsoc_afc_ctrl) | in sirfsoc_uart_enable_ms()
367 if (!sirfport->is_atlas7) in sirfsoc_uart_enable_ms()
368 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_enable_ms()
369 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_enable_ms()
370 | uint_en->sirfsoc_cts_en); in sirfsoc_uart_enable_ms()
372 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_enable_ms()
373 uint_en->sirfsoc_cts_en); in sirfsoc_uart_enable_ms()
375 enable_irq(gpio_to_irq(sirfport->cts_gpio)); in sirfsoc_uart_enable_ms()
381 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_break_ctl()
382 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { in sirfsoc_uart_break_ctl()
383 unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl); in sirfsoc_uart_break_ctl()
388 wr_regl(port, ureg->sirfsoc_line_ctrl, ulcon); in sirfsoc_uart_break_ctl()
396 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_pio_rx_chars()
397 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; in sirfsoc_uart_pio_rx_chars()
400 tty = tty_port_tty_get(&port->state->port); in sirfsoc_uart_pio_rx_chars()
402 return -ENODEV; in sirfsoc_uart_pio_rx_chars()
403 while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) & in sirfsoc_uart_pio_rx_chars()
404 ufifo_st->ff_empty(port))) { in sirfsoc_uart_pio_rx_chars()
405 ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) | in sirfsoc_uart_pio_rx_chars()
415 port->icount.rx += rx_count; in sirfsoc_uart_pio_rx_chars()
423 struct uart_port *port = &sirfport->port; in sirfsoc_uart_pio_tx_chars()
424 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_pio_tx_chars()
425 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; in sirfsoc_uart_pio_tx_chars()
426 struct circ_buf *xmit = &port->state->xmit; in sirfsoc_uart_pio_tx_chars()
429 !(rd_regl(port, ureg->sirfsoc_tx_fifo_status) & in sirfsoc_uart_pio_tx_chars()
430 ufifo_st->ff_full(port)) && in sirfsoc_uart_pio_tx_chars()
431 count--) { in sirfsoc_uart_pio_tx_chars()
432 wr_regl(port, ureg->sirfsoc_tx_fifo_data, in sirfsoc_uart_pio_tx_chars()
433 xmit->buf[xmit->tail]); in sirfsoc_uart_pio_tx_chars()
434 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in sirfsoc_uart_pio_tx_chars()
435 port->icount.tx++; in sirfsoc_uart_pio_tx_chars()
446 struct uart_port *port = &sirfport->port; in sirfsoc_uart_tx_dma_complete_callback()
447 struct circ_buf *xmit = &port->state->xmit; in sirfsoc_uart_tx_dma_complete_callback()
450 spin_lock_irqsave(&port->lock, flags); in sirfsoc_uart_tx_dma_complete_callback()
451 xmit->tail = (xmit->tail + sirfport->transfer_size) & in sirfsoc_uart_tx_dma_complete_callback()
452 (UART_XMIT_SIZE - 1); in sirfsoc_uart_tx_dma_complete_callback()
453 port->icount.tx += sirfport->transfer_size; in sirfsoc_uart_tx_dma_complete_callback()
456 if (sirfport->tx_dma_addr) in sirfsoc_uart_tx_dma_complete_callback()
457 dma_unmap_single(port->dev, sirfport->tx_dma_addr, in sirfsoc_uart_tx_dma_complete_callback()
458 sirfport->transfer_size, DMA_TO_DEVICE); in sirfsoc_uart_tx_dma_complete_callback()
459 sirfport->tx_dma_state = TX_DMA_IDLE; in sirfsoc_uart_tx_dma_complete_callback()
461 spin_unlock_irqrestore(&port->lock, flags); in sirfsoc_uart_tx_dma_complete_callback()
470 struct uart_port *port = &sirfport->port; in sirfsoc_uart_isr()
471 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_isr()
472 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; in sirfsoc_uart_isr()
473 struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st; in sirfsoc_uart_isr()
474 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; in sirfsoc_uart_isr()
475 struct uart_state *state = port->state; in sirfsoc_uart_isr()
476 struct circ_buf *xmit = &port->state->xmit; in sirfsoc_uart_isr()
477 spin_lock(&port->lock); in sirfsoc_uart_isr()
478 intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg); in sirfsoc_uart_isr()
479 wr_regl(port, ureg->sirfsoc_int_st_reg, intr_status); in sirfsoc_uart_isr()
480 intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg); in sirfsoc_uart_isr()
482 sirfport->uart_reg->uart_type)))) { in sirfsoc_uart_isr()
483 if (intr_status & uint_st->sirfsoc_rxd_brk) { in sirfsoc_uart_isr()
484 port->icount.brk++; in sirfsoc_uart_isr()
488 if (intr_status & uint_st->sirfsoc_rx_oflow) { in sirfsoc_uart_isr()
489 port->icount.overrun++; in sirfsoc_uart_isr()
492 if (intr_status & uint_st->sirfsoc_frm_err) { in sirfsoc_uart_isr()
493 port->icount.frame++; in sirfsoc_uart_isr()
496 if (intr_status & uint_st->sirfsoc_parity_err) { in sirfsoc_uart_isr()
497 port->icount.parity++; in sirfsoc_uart_isr()
500 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET); in sirfsoc_uart_isr()
501 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0); in sirfsoc_uart_isr()
502 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START); in sirfsoc_uart_isr()
503 intr_status &= port->read_status_mask; in sirfsoc_uart_isr()
505 uint_en->sirfsoc_rx_oflow_en, 0, flag); in sirfsoc_uart_isr()
508 if ((sirfport->uart_reg->uart_type == SIRF_REAL_UART) && in sirfsoc_uart_isr()
510 !sirfport->tx_dma_state) { in sirfsoc_uart_isr()
511 cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) & in sirfsoc_uart_isr()
518 wake_up_interruptible(&state->port.delta_msr_wait); in sirfsoc_uart_isr()
520 if (!sirfport->rx_dma_chan && in sirfsoc_uart_isr()
532 if (intr_status & uint_st->sirfsoc_rx_done) { in sirfsoc_uart_isr()
533 if (!sirfport->is_atlas7) { in sirfsoc_uart_isr()
534 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_isr()
535 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_isr()
536 & ~(uint_en->sirfsoc_rx_done_en)); in sirfsoc_uart_isr()
537 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_isr()
538 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_isr()
539 | (uint_en->sirfsoc_rx_timeout_en)); in sirfsoc_uart_isr()
541 wr_regl(port, ureg->sirfsoc_int_en_clr_reg, in sirfsoc_uart_isr()
542 uint_en->sirfsoc_rx_done_en); in sirfsoc_uart_isr()
543 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_isr()
544 uint_en->sirfsoc_rx_timeout_en); in sirfsoc_uart_isr()
547 if (intr_status & uint_st->sirfsoc_rx_timeout) { in sirfsoc_uart_isr()
548 if (!sirfport->is_atlas7) { in sirfsoc_uart_isr()
549 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_isr()
550 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_isr()
551 & ~(uint_en->sirfsoc_rx_timeout_en)); in sirfsoc_uart_isr()
552 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_isr()
553 rd_regl(port, ureg->sirfsoc_int_en_reg) in sirfsoc_uart_isr()
554 | (uint_en->sirfsoc_rx_done_en)); in sirfsoc_uart_isr()
557 ureg->sirfsoc_int_en_clr_reg, in sirfsoc_uart_isr()
558 uint_en->sirfsoc_rx_timeout_en); in sirfsoc_uart_isr()
559 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_isr()
560 uint_en->sirfsoc_rx_done_en); in sirfsoc_uart_isr()
563 sirfsoc_uart_pio_rx_chars(port, port->fifosize); in sirfsoc_uart_isr()
566 spin_unlock(&port->lock); in sirfsoc_uart_isr()
567 tty_flip_buffer_push(&state->port); in sirfsoc_uart_isr()
568 spin_lock(&port->lock); in sirfsoc_uart_isr()
569 if (intr_status & uint_st->sirfsoc_txfifo_empty) { in sirfsoc_uart_isr()
570 if (sirfport->tx_dma_chan) in sirfsoc_uart_isr()
574 spin_unlock(&port->lock); in sirfsoc_uart_isr()
578 port->fifosize); in sirfsoc_uart_isr()
580 (rd_regl(port, ureg->sirfsoc_tx_fifo_status) & in sirfsoc_uart_isr()
581 ufifo_st->ff_empty(port))) in sirfsoc_uart_isr()
586 spin_unlock(&port->lock); in sirfsoc_uart_isr()
599 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_start_next_rx_dma()
600 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; in sirfsoc_uart_start_next_rx_dma()
601 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, in sirfsoc_uart_start_next_rx_dma()
602 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & in sirfsoc_uart_start_next_rx_dma()
604 sirfport->rx_dma_items.xmit.tail = in sirfsoc_uart_start_next_rx_dma()
605 sirfport->rx_dma_items.xmit.head = 0; in sirfsoc_uart_start_next_rx_dma()
606 sirfport->rx_dma_items.desc = in sirfsoc_uart_start_next_rx_dma()
607 dmaengine_prep_dma_cyclic(sirfport->rx_dma_chan, in sirfsoc_uart_start_next_rx_dma()
608 sirfport->rx_dma_items.dma_addr, SIRFSOC_RX_DMA_BUF_SIZE, in sirfsoc_uart_start_next_rx_dma()
611 if (IS_ERR_OR_NULL(sirfport->rx_dma_items.desc)) { in sirfsoc_uart_start_next_rx_dma()
612 dev_err(port->dev, "DMA slave single fail\n"); in sirfsoc_uart_start_next_rx_dma()
615 sirfport->rx_dma_items.desc->callback = in sirfsoc_uart_start_next_rx_dma()
617 sirfport->rx_dma_items.desc->callback_param = sirfport; in sirfsoc_uart_start_next_rx_dma()
618 sirfport->rx_dma_items.cookie = in sirfsoc_uart_start_next_rx_dma()
619 dmaengine_submit(sirfport->rx_dma_items.desc); in sirfsoc_uart_start_next_rx_dma()
620 dma_async_issue_pending(sirfport->rx_dma_chan); in sirfsoc_uart_start_next_rx_dma()
621 if (!sirfport->is_atlas7) in sirfsoc_uart_start_next_rx_dma()
622 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_start_next_rx_dma()
623 rd_regl(port, ureg->sirfsoc_int_en_reg) | in sirfsoc_uart_start_next_rx_dma()
625 sirfport->uart_reg->uart_type)); in sirfsoc_uart_start_next_rx_dma()
627 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_start_next_rx_dma()
629 sirfport->uart_reg->uart_type)); in sirfsoc_uart_start_next_rx_dma()
643 temp_delta = ioclk_rate - in sirfsoc_usp_calc_sample_div()
647 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta; in sirfsoc_usp_calc_sample_div()
650 (set_rate * sample_div) + 1) / 2 - 1; in sirfsoc_usp_calc_sample_div()
675 ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1; in sirfsoc_uart_calc_sample_div()
679 temp_delta = baud_tmp - baud_rate; in sirfsoc_uart_calc_sample_div()
680 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta; in sirfsoc_uart_calc_sample_div()
698 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_set_termios()
699 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; in sirfsoc_uart_set_termios()
711 ioclk_rate = port->uartclk; in sirfsoc_uart_set_termios()
713 switch (termios->c_cflag & CSIZE) { in sirfsoc_uart_set_termios()
732 if (termios->c_cflag & CSTOPB) { in sirfsoc_uart_set_termios()
738 spin_lock_irqsave(&port->lock, flags); in sirfsoc_uart_set_termios()
739 port->read_status_mask = uint_en->sirfsoc_rx_oflow_en; in sirfsoc_uart_set_termios()
740 port->ignore_status_mask = 0; in sirfsoc_uart_set_termios()
741 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { in sirfsoc_uart_set_termios()
742 if (termios->c_iflag & INPCK) in sirfsoc_uart_set_termios()
743 port->read_status_mask |= uint_en->sirfsoc_frm_err_en | in sirfsoc_uart_set_termios()
744 uint_en->sirfsoc_parity_err_en; in sirfsoc_uart_set_termios()
746 if (termios->c_iflag & INPCK) in sirfsoc_uart_set_termios()
747 port->read_status_mask |= uint_en->sirfsoc_frm_err_en; in sirfsoc_uart_set_termios()
749 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in sirfsoc_uart_set_termios()
750 port->read_status_mask |= uint_en->sirfsoc_rxd_brk_en; in sirfsoc_uart_set_termios()
751 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { in sirfsoc_uart_set_termios()
752 if (termios->c_iflag & IGNPAR) in sirfsoc_uart_set_termios()
753 port->ignore_status_mask |= in sirfsoc_uart_set_termios()
754 uint_en->sirfsoc_frm_err_en | in sirfsoc_uart_set_termios()
755 uint_en->sirfsoc_parity_err_en; in sirfsoc_uart_set_termios()
756 if (termios->c_cflag & PARENB) { in sirfsoc_uart_set_termios()
757 if (termios->c_cflag & CMSPAR) { in sirfsoc_uart_set_termios()
758 if (termios->c_cflag & PARODD) in sirfsoc_uart_set_termios()
763 if (termios->c_cflag & PARODD) in sirfsoc_uart_set_termios()
770 if (termios->c_iflag & IGNPAR) in sirfsoc_uart_set_termios()
771 port->ignore_status_mask |= in sirfsoc_uart_set_termios()
772 uint_en->sirfsoc_frm_err_en; in sirfsoc_uart_set_termios()
773 if (termios->c_cflag & PARENB) in sirfsoc_uart_set_termios()
774 dev_warn(port->dev, in sirfsoc_uart_set_termios()
775 "USP-UART not support parity err\n"); in sirfsoc_uart_set_termios()
777 if (termios->c_iflag & IGNBRK) { in sirfsoc_uart_set_termios()
778 port->ignore_status_mask |= in sirfsoc_uart_set_termios()
779 uint_en->sirfsoc_rxd_brk_en; in sirfsoc_uart_set_termios()
780 if (termios->c_iflag & IGNPAR) in sirfsoc_uart_set_termios()
781 port->ignore_status_mask |= in sirfsoc_uart_set_termios()
782 uint_en->sirfsoc_rx_oflow_en; in sirfsoc_uart_set_termios()
784 if ((termios->c_cflag & CREAD) == 0) in sirfsoc_uart_set_termios()
785 port->ignore_status_mask |= SIRFUART_DUMMY_READ; in sirfsoc_uart_set_termios()
787 if (UART_ENABLE_MS(port, termios->c_cflag)) { in sirfsoc_uart_set_termios()
788 if (!sirfport->ms_enabled) in sirfsoc_uart_set_termios()
791 if (sirfport->ms_enabled) in sirfsoc_uart_set_termios()
801 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { in sirfsoc_uart_set_termios()
805 wr_regl(port, ureg->sirfsoc_divisor, clk_div_reg); in sirfsoc_uart_set_termios()
809 sample_div_reg--; in sirfsoc_uart_set_termios()
810 set_baud = ((ioclk_rate / (clk_div_reg+1) - 1) / in sirfsoc_uart_set_termios()
817 wr_regl(port, ureg->sirfsoc_mode2, len_val); in sirfsoc_uart_set_termios()
824 txfifo_op_reg = rd_regl(port, ureg->sirfsoc_tx_fifo_op); in sirfsoc_uart_set_termios()
825 wr_regl(port, ureg->sirfsoc_tx_fifo_op, in sirfsoc_uart_set_termios()
827 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { in sirfsoc_uart_set_termios()
829 wr_regl(port, ureg->sirfsoc_line_ctrl, config_reg); in sirfsoc_uart_set_termios()
832 len_val = (data_bit_len - 1) << SIRFSOC_USP_TX_DATA_LEN_OFFSET; in sirfsoc_uart_set_termios()
833 len_val |= (data_bit_len + 1 + stop_bit_len - 1) << in sirfsoc_uart_set_termios()
835 len_val |= ((data_bit_len - 1) << in sirfsoc_uart_set_termios()
839 wr_regl(port, ureg->sirfsoc_tx_frame_ctrl, len_val); in sirfsoc_uart_set_termios()
841 len_val = (data_bit_len - 1) << SIRFSOC_USP_RX_DATA_LEN_OFFSET; in sirfsoc_uart_set_termios()
842 len_val |= (data_bit_len + 1 + stop_bit_len - 1) << in sirfsoc_uart_set_termios()
844 len_val |= (data_bit_len - 1) << in sirfsoc_uart_set_termios()
848 wr_regl(port, ureg->sirfsoc_rx_frame_ctrl, len_val); in sirfsoc_uart_set_termios()
850 wr_regl(port, ureg->sirfsoc_async_param_reg, in sirfsoc_uart_set_termios()
855 if (sirfport->tx_dma_chan) in sirfsoc_uart_set_termios()
856 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_DMA_MODE); in sirfsoc_uart_set_termios()
858 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_IO_MODE); in sirfsoc_uart_set_termios()
859 if (sirfport->rx_dma_chan) in sirfsoc_uart_set_termios()
860 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, in sirfsoc_uart_set_termios()
861 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & in sirfsoc_uart_set_termios()
864 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, in sirfsoc_uart_set_termios()
865 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | in sirfsoc_uart_set_termios()
867 sirfport->rx_period_time = 20000000; in sirfsoc_uart_set_termios()
873 wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, in sirfsoc_uart_set_termios()
875 wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, in sirfsoc_uart_set_termios()
878 wr_regl(port, ureg->sirfsoc_tx_fifo_op, txfifo_op_reg); in sirfsoc_uart_set_termios()
879 uart_update_timeout(port, termios->c_cflag, set_baud); in sirfsoc_uart_set_termios()
880 wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_TX_EN | SIRFUART_RX_EN); in sirfsoc_uart_set_termios()
881 spin_unlock_irqrestore(&port->lock, flags); in sirfsoc_uart_set_termios()
889 clk_prepare_enable(sirfport->clk); in sirfsoc_uart_pm()
891 clk_disable_unprepare(sirfport->clk); in sirfsoc_uart_pm()
897 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_startup()
898 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; in sirfsoc_uart_startup()
899 unsigned int index = port->line; in sirfsoc_uart_startup()
901 irq_modify_status(port->irq, IRQ_NOREQUEST, IRQ_NOAUTOEN); in sirfsoc_uart_startup()
902 ret = request_irq(port->irq, in sirfsoc_uart_startup()
908 dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n", in sirfsoc_uart_startup()
909 index, port->irq); in sirfsoc_uart_startup()
913 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, in sirfsoc_uart_startup()
914 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl) | in sirfsoc_uart_startup()
916 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, in sirfsoc_uart_startup()
917 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | in sirfsoc_uart_startup()
919 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, in sirfsoc_uart_startup()
920 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & in sirfsoc_uart_startup()
922 wr_regl(port, ureg->sirfsoc_tx_dma_io_len, 0); in sirfsoc_uart_startup()
923 wr_regl(port, ureg->sirfsoc_rx_dma_io_len, 0); in sirfsoc_uart_startup()
924 wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_RX_EN | SIRFUART_TX_EN); in sirfsoc_uart_startup()
925 if (sirfport->uart_reg->uart_type == SIRF_USP_UART) in sirfsoc_uart_startup()
926 wr_regl(port, ureg->sirfsoc_mode1, in sirfsoc_uart_startup()
929 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_RESET); in sirfsoc_uart_startup()
930 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET); in sirfsoc_uart_startup()
931 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0); in sirfsoc_uart_startup()
932 wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, SIRFUART_FIFO_THD(port)); in sirfsoc_uart_startup()
933 wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, SIRFUART_FIFO_THD(port)); in sirfsoc_uart_startup()
934 if (sirfport->rx_dma_chan) in sirfsoc_uart_startup()
935 wr_regl(port, ureg->sirfsoc_rx_fifo_level_chk, in sirfsoc_uart_startup()
936 SIRFUART_RX_FIFO_CHK_SC(port->line, 0x1) | in sirfsoc_uart_startup()
937 SIRFUART_RX_FIFO_CHK_LC(port->line, 0x2) | in sirfsoc_uart_startup()
938 SIRFUART_RX_FIFO_CHK_HC(port->line, 0x4)); in sirfsoc_uart_startup()
939 if (sirfport->tx_dma_chan) { in sirfsoc_uart_startup()
940 sirfport->tx_dma_state = TX_DMA_IDLE; in sirfsoc_uart_startup()
941 wr_regl(port, ureg->sirfsoc_tx_fifo_level_chk, in sirfsoc_uart_startup()
942 SIRFUART_TX_FIFO_CHK_SC(port->line, 0x1b) | in sirfsoc_uart_startup()
943 SIRFUART_TX_FIFO_CHK_LC(port->line, 0xe) | in sirfsoc_uart_startup()
944 SIRFUART_TX_FIFO_CHK_HC(port->line, 0x4)); in sirfsoc_uart_startup()
946 sirfport->ms_enabled = false; in sirfsoc_uart_startup()
947 if (sirfport->uart_reg->uart_type == SIRF_USP_UART && in sirfsoc_uart_startup()
948 sirfport->hw_flow_ctrl) { in sirfsoc_uart_startup()
949 irq_modify_status(gpio_to_irq(sirfport->cts_gpio), in sirfsoc_uart_startup()
951 ret = request_irq(gpio_to_irq(sirfport->cts_gpio), in sirfsoc_uart_startup()
955 dev_err(port->dev, "UART-USP:request gpio irq fail\n"); in sirfsoc_uart_startup()
959 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART && in sirfsoc_uart_startup()
960 sirfport->rx_dma_chan) in sirfsoc_uart_startup()
961 wr_regl(port, ureg->sirfsoc_swh_dma_io, in sirfsoc_uart_startup()
963 if (sirfport->uart_reg->uart_type == SIRF_USP_UART && in sirfsoc_uart_startup()
964 sirfport->rx_dma_chan) in sirfsoc_uart_startup()
965 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, in sirfsoc_uart_startup()
966 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | in sirfsoc_uart_startup()
968 if (sirfport->rx_dma_chan && !sirfport->is_hrt_enabled) { in sirfsoc_uart_startup()
969 sirfport->is_hrt_enabled = true; in sirfsoc_uart_startup()
970 sirfport->rx_period_time = 20000000; in sirfsoc_uart_startup()
971 sirfport->rx_last_pos = -1; in sirfsoc_uart_startup()
972 sirfport->pio_fetch_cnt = 0; in sirfsoc_uart_startup()
973 sirfport->rx_dma_items.xmit.tail = in sirfsoc_uart_startup()
974 sirfport->rx_dma_items.xmit.head = 0; in sirfsoc_uart_startup()
975 hrtimer_start(&sirfport->hrt, in sirfsoc_uart_startup()
976 ns_to_ktime(sirfport->rx_period_time), in sirfsoc_uart_startup()
979 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START); in sirfsoc_uart_startup()
980 if (sirfport->rx_dma_chan) in sirfsoc_uart_startup()
983 if (!sirfport->is_atlas7) in sirfsoc_uart_startup()
984 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_startup()
985 rd_regl(port, ureg->sirfsoc_int_en_reg) | in sirfsoc_uart_startup()
987 sirfport->uart_reg->uart_type)); in sirfsoc_uart_startup()
989 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_startup()
991 sirfport->uart_reg->uart_type)); in sirfsoc_uart_startup()
993 enable_irq(port->irq); in sirfsoc_uart_startup()
997 free_irq(port->irq, sirfport); in sirfsoc_uart_startup()
1005 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_shutdown()
1008 xmit = &sirfport->rx_dma_items.xmit; in sirfsoc_uart_shutdown()
1009 if (!sirfport->is_atlas7) in sirfsoc_uart_shutdown()
1010 wr_regl(port, ureg->sirfsoc_int_en_reg, 0); in sirfsoc_uart_shutdown()
1012 wr_regl(port, ureg->sirfsoc_int_en_clr_reg, ~0UL); in sirfsoc_uart_shutdown()
1014 free_irq(port->irq, sirfport); in sirfsoc_uart_shutdown()
1015 if (sirfport->ms_enabled) in sirfsoc_uart_shutdown()
1017 if (sirfport->uart_reg->uart_type == SIRF_USP_UART && in sirfsoc_uart_shutdown()
1018 sirfport->hw_flow_ctrl) { in sirfsoc_uart_shutdown()
1019 gpio_set_value(sirfport->rts_gpio, 1); in sirfsoc_uart_shutdown()
1020 free_irq(gpio_to_irq(sirfport->cts_gpio), sirfport); in sirfsoc_uart_shutdown()
1022 if (sirfport->tx_dma_chan) in sirfsoc_uart_shutdown()
1023 sirfport->tx_dma_state = TX_DMA_IDLE; in sirfsoc_uart_shutdown()
1024 if (sirfport->rx_dma_chan && sirfport->is_hrt_enabled) { in sirfsoc_uart_shutdown()
1025 while (((rd_regl(port, ureg->sirfsoc_rx_fifo_status) & in sirfsoc_uart_shutdown()
1026 SIRFUART_RX_FIFO_MASK) > sirfport->pio_fetch_cnt) && in sirfsoc_uart_shutdown()
1027 !CIRC_CNT(xmit->head, xmit->tail, in sirfsoc_uart_shutdown()
1030 sirfport->is_hrt_enabled = false; in sirfsoc_uart_shutdown()
1031 hrtimer_cancel(&sirfport->hrt); in sirfsoc_uart_shutdown()
1037 return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL; in sirfsoc_uart_type()
1043 struct sirfsoc_uart_param *uart_param = &sirfport->uart_reg->uart_param; in sirfsoc_uart_request_port()
1045 ret = request_mem_region(port->mapbase, in sirfsoc_uart_request_port()
1046 SIRFUART_MAP_SIZE, uart_param->port_name); in sirfsoc_uart_request_port()
1047 return ret ? 0 : -EBUSY; in sirfsoc_uart_request_port()
1052 release_mem_region(port->mapbase, SIRFUART_MAP_SIZE); in sirfsoc_uart_release_port()
1058 port->type = SIRFSOC_PORT_TYPE; in sirfsoc_uart_config_port()
1092 if (co->index < 0 || co->index >= SIRFSOC_UART_NR) in sirfsoc_uart_console_setup()
1093 co->index = 1; in sirfsoc_uart_console_setup()
1094 sirfport = sirf_ports[co->index]; in sirfsoc_uart_console_setup()
1096 return -ENODEV; in sirfsoc_uart_console_setup()
1097 ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_console_setup()
1098 if (!sirfport->port.mapbase) in sirfsoc_uart_console_setup()
1099 return -ENODEV; in sirfsoc_uart_console_setup()
1102 if (sirfport->uart_reg->uart_type == SIRF_USP_UART) in sirfsoc_uart_console_setup()
1103 wr_regl(&sirfport->port, ureg->sirfsoc_mode1, SIRFSOC_USP_EN | in sirfsoc_uart_console_setup()
1107 sirfport->port.cons = co; in sirfsoc_uart_console_setup()
1110 sirfport->rx_dma_chan = NULL; in sirfsoc_uart_console_setup()
1111 sirfport->tx_dma_chan = NULL; in sirfsoc_uart_console_setup()
1112 return uart_set_options(&sirfport->port, co, baud, parity, bits, flow); in sirfsoc_uart_console_setup()
1118 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_console_putchar()
1119 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; in sirfsoc_uart_console_putchar()
1120 while (rd_regl(port, ureg->sirfsoc_tx_fifo_status) & in sirfsoc_uart_console_putchar()
1121 ufifo_st->ff_full(port)) in sirfsoc_uart_console_putchar()
1123 wr_regl(port, ureg->sirfsoc_tx_fifo_data, ch); in sirfsoc_uart_console_putchar()
1129 struct sirfsoc_uart_port *sirfport = sirf_ports[co->index]; in sirfsoc_uart_console_write()
1131 uart_console_write(&sirfport->port, s, count, in sirfsoc_uart_console_write()
1139 .index = -1,
1181 port = &sirfport->port; in sirfsoc_uart_rx_dma_hrtimer_callback()
1183 tty = port->state->port.tty; in sirfsoc_uart_rx_dma_hrtimer_callback()
1184 ureg = &sirfport->uart_reg->uart_reg; in sirfsoc_uart_rx_dma_hrtimer_callback()
1185 xmit = &sirfport->rx_dma_items.xmit; in sirfsoc_uart_rx_dma_hrtimer_callback()
1186 ufifo_st = &sirfport->uart_reg->fifo_status; in sirfsoc_uart_rx_dma_hrtimer_callback()
1188 dmaengine_tx_status(sirfport->rx_dma_chan, in sirfsoc_uart_rx_dma_hrtimer_callback()
1189 sirfport->rx_dma_items.cookie, &tx_state); in sirfsoc_uart_rx_dma_hrtimer_callback()
1190 if (SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue != in sirfsoc_uart_rx_dma_hrtimer_callback()
1191 sirfport->rx_last_pos) { in sirfsoc_uart_rx_dma_hrtimer_callback()
1192 xmit->head = SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue; in sirfsoc_uart_rx_dma_hrtimer_callback()
1193 sirfport->rx_last_pos = xmit->head; in sirfsoc_uart_rx_dma_hrtimer_callback()
1194 sirfport->pio_fetch_cnt = 0; in sirfsoc_uart_rx_dma_hrtimer_callback()
1196 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, in sirfsoc_uart_rx_dma_hrtimer_callback()
1199 inserted = tty_insert_flip_string(tty->port, in sirfsoc_uart_rx_dma_hrtimer_callback()
1200 (const unsigned char *)&xmit->buf[xmit->tail], count); in sirfsoc_uart_rx_dma_hrtimer_callback()
1203 port->icount.rx += inserted; in sirfsoc_uart_rx_dma_hrtimer_callback()
1204 xmit->tail = (xmit->tail + inserted) & in sirfsoc_uart_rx_dma_hrtimer_callback()
1205 (SIRFSOC_RX_DMA_BUF_SIZE - 1); in sirfsoc_uart_rx_dma_hrtimer_callback()
1206 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, in sirfsoc_uart_rx_dma_hrtimer_callback()
1208 tty_flip_buffer_push(tty->port); in sirfsoc_uart_rx_dma_hrtimer_callback()
1216 ((rd_regl(port, ureg->sirfsoc_rx_fifo_status) & in sirfsoc_uart_rx_dma_hrtimer_callback()
1217 SIRFUART_RX_FIFO_MASK) > sirfport->pio_fetch_cnt)) { in sirfsoc_uart_rx_dma_hrtimer_callback()
1218 dmaengine_pause(sirfport->rx_dma_chan); in sirfsoc_uart_rx_dma_hrtimer_callback()
1220 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, in sirfsoc_uart_rx_dma_hrtimer_callback()
1221 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | in sirfsoc_uart_rx_dma_hrtimer_callback()
1229 * while switch back to DMA mode, the data fetched will override in sirfsoc_uart_rx_dma_hrtimer_callback()
1236 while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) & in sirfsoc_uart_rx_dma_hrtimer_callback()
1237 ufifo_st->ff_empty(port)) && max_pio_cnt--) { in sirfsoc_uart_rx_dma_hrtimer_callback()
1238 xmit->buf[xmit->head] = in sirfsoc_uart_rx_dma_hrtimer_callback()
1239 rd_regl(port, ureg->sirfsoc_rx_fifo_data); in sirfsoc_uart_rx_dma_hrtimer_callback()
1240 xmit->head = (xmit->head + 1) & in sirfsoc_uart_rx_dma_hrtimer_callback()
1241 (SIRFSOC_RX_DMA_BUF_SIZE - 1); in sirfsoc_uart_rx_dma_hrtimer_callback()
1242 sirfport->pio_fetch_cnt++; in sirfsoc_uart_rx_dma_hrtimer_callback()
1245 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, in sirfsoc_uart_rx_dma_hrtimer_callback()
1246 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & in sirfsoc_uart_rx_dma_hrtimer_callback()
1248 dmaengine_resume(sirfport->rx_dma_chan); in sirfsoc_uart_rx_dma_hrtimer_callback()
1251 hrtimer_forward_now(hrt, ns_to_ktime(sirfport->rx_period_time)); in sirfsoc_uart_rx_dma_hrtimer_callback()
1256 { .compatible = "sirf,prima2-uart", .data = &sirfsoc_uart,},
1257 { .compatible = "sirf,atlas7-uart", .data = &sirfsoc_uart},
1258 { .compatible = "sirf,prima2-usp-uart", .data = &sirfsoc_usp},
1259 { .compatible = "sirf,atlas7-usp-uart", .data = &sirfsoc_usp},
1266 struct device_node *np = pdev->dev.of_node; in sirfsoc_uart_probe()
1280 sirfport = devm_kzalloc(&pdev->dev, sizeof(*sirfport), GFP_KERNEL); in sirfsoc_uart_probe()
1282 ret = -ENOMEM; in sirfsoc_uart_probe()
1285 sirfport->port.line = of_alias_get_id(np, "serial"); in sirfsoc_uart_probe()
1286 if (sirfport->port.line >= ARRAY_SIZE(sirf_ports)) { in sirfsoc_uart_probe()
1287 dev_err(&pdev->dev, "serial%d out of range\n", in sirfsoc_uart_probe()
1288 sirfport->port.line); in sirfsoc_uart_probe()
1289 return -EINVAL; in sirfsoc_uart_probe()
1291 sirf_ports[sirfport->port.line] = sirfport; in sirfsoc_uart_probe()
1292 sirfport->port.iotype = UPIO_MEM; in sirfsoc_uart_probe()
1293 sirfport->port.flags = UPF_BOOT_AUTOCONF; in sirfsoc_uart_probe()
1294 port = &sirfport->port; in sirfsoc_uart_probe()
1295 port->dev = &pdev->dev; in sirfsoc_uart_probe()
1296 port->private_data = sirfport; in sirfsoc_uart_probe()
1297 sirfport->uart_reg = (struct sirfsoc_uart_register *)match->data; in sirfsoc_uart_probe()
1299 sirfport->hw_flow_ctrl = in sirfsoc_uart_probe()
1300 of_property_read_bool(np, "uart-has-rtscts") || in sirfsoc_uart_probe()
1301 of_property_read_bool(np, "sirf,uart-has-rtscts") /* deprecated */; in sirfsoc_uart_probe()
1302 if (of_device_is_compatible(np, "sirf,prima2-uart") || in sirfsoc_uart_probe()
1303 of_device_is_compatible(np, "sirf,atlas7-uart")) in sirfsoc_uart_probe()
1304 sirfport->uart_reg->uart_type = SIRF_REAL_UART; in sirfsoc_uart_probe()
1305 if (of_device_is_compatible(np, "sirf,prima2-usp-uart") || in sirfsoc_uart_probe()
1306 of_device_is_compatible(np, "sirf,atlas7-usp-uart")) { in sirfsoc_uart_probe()
1307 sirfport->uart_reg->uart_type = SIRF_USP_UART; in sirfsoc_uart_probe()
1308 if (!sirfport->hw_flow_ctrl) in sirfsoc_uart_probe()
1310 if (of_find_property(np, "cts-gpios", NULL)) in sirfsoc_uart_probe()
1311 sirfport->cts_gpio = in sirfsoc_uart_probe()
1312 of_get_named_gpio(np, "cts-gpios", 0); in sirfsoc_uart_probe()
1314 sirfport->cts_gpio = -1; in sirfsoc_uart_probe()
1315 if (of_find_property(np, "rts-gpios", NULL)) in sirfsoc_uart_probe()
1316 sirfport->rts_gpio = in sirfsoc_uart_probe()
1317 of_get_named_gpio(np, "rts-gpios", 0); in sirfsoc_uart_probe()
1319 sirfport->rts_gpio = -1; in sirfsoc_uart_probe()
1321 if ((!gpio_is_valid(sirfport->cts_gpio) || in sirfsoc_uart_probe()
1322 !gpio_is_valid(sirfport->rts_gpio))) { in sirfsoc_uart_probe()
1323 ret = -EINVAL; in sirfsoc_uart_probe()
1324 dev_err(&pdev->dev, in sirfsoc_uart_probe()
1325 "Usp flow control must have cts and rts gpio"); in sirfsoc_uart_probe()
1328 ret = devm_gpio_request(&pdev->dev, sirfport->cts_gpio, in sirfsoc_uart_probe()
1329 "usp-cts-gpio"); in sirfsoc_uart_probe()
1331 dev_err(&pdev->dev, "Unable request cts gpio"); in sirfsoc_uart_probe()
1334 gpio_direction_input(sirfport->cts_gpio); in sirfsoc_uart_probe()
1335 ret = devm_gpio_request(&pdev->dev, sirfport->rts_gpio, in sirfsoc_uart_probe()
1336 "usp-rts-gpio"); in sirfsoc_uart_probe()
1338 dev_err(&pdev->dev, "Unable request rts gpio"); in sirfsoc_uart_probe()
1341 gpio_direction_output(sirfport->rts_gpio, 1); in sirfsoc_uart_probe()
1344 if (of_device_is_compatible(np, "sirf,atlas7-uart") || in sirfsoc_uart_probe()
1345 of_device_is_compatible(np, "sirf,atlas7-usp-uart")) in sirfsoc_uart_probe()
1346 sirfport->is_atlas7 = true; in sirfsoc_uart_probe()
1348 if (of_property_read_u32(np, "fifosize", &port->fifosize)) { in sirfsoc_uart_probe()
1349 dev_err(&pdev->dev, in sirfsoc_uart_probe()
1351 ret = -EFAULT; in sirfsoc_uart_probe()
1357 dev_err(&pdev->dev, "Insufficient resources.\n"); in sirfsoc_uart_probe()
1358 ret = -EFAULT; in sirfsoc_uart_probe()
1361 port->mapbase = res->start; in sirfsoc_uart_probe()
1362 port->membase = devm_ioremap(&pdev->dev, in sirfsoc_uart_probe()
1363 res->start, resource_size(res)); in sirfsoc_uart_probe()
1364 if (!port->membase) { in sirfsoc_uart_probe()
1365 dev_err(&pdev->dev, "Cannot remap resource.\n"); in sirfsoc_uart_probe()
1366 ret = -ENOMEM; in sirfsoc_uart_probe()
1371 dev_err(&pdev->dev, "Insufficient resources.\n"); in sirfsoc_uart_probe()
1372 ret = -EFAULT; in sirfsoc_uart_probe()
1375 port->irq = res->start; in sirfsoc_uart_probe()
1377 sirfport->clk = devm_clk_get(&pdev->dev, NULL); in sirfsoc_uart_probe()
1378 if (IS_ERR(sirfport->clk)) { in sirfsoc_uart_probe()
1379 ret = PTR_ERR(sirfport->clk); in sirfsoc_uart_probe()
1382 port->uartclk = clk_get_rate(sirfport->clk); in sirfsoc_uart_probe()
1384 port->ops = &sirfsoc_uart_ops; in sirfsoc_uart_probe()
1385 spin_lock_init(&port->lock); in sirfsoc_uart_probe()
1390 dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id); in sirfsoc_uart_probe()
1394 sirfport->rx_dma_chan = dma_request_slave_channel(port->dev, "rx"); in sirfsoc_uart_probe()
1395 sirfport->rx_dma_items.xmit.buf = in sirfsoc_uart_probe()
1396 dma_alloc_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE, in sirfsoc_uart_probe()
1397 &sirfport->rx_dma_items.dma_addr, GFP_KERNEL); in sirfsoc_uart_probe()
1398 if (!sirfport->rx_dma_items.xmit.buf) { in sirfsoc_uart_probe()
1399 dev_err(port->dev, "Uart alloc bufa failed\n"); in sirfsoc_uart_probe()
1400 ret = -ENOMEM; in sirfsoc_uart_probe()
1403 sirfport->rx_dma_items.xmit.head = in sirfsoc_uart_probe()
1404 sirfport->rx_dma_items.xmit.tail = 0; in sirfsoc_uart_probe()
1405 if (sirfport->rx_dma_chan) in sirfsoc_uart_probe()
1406 dmaengine_slave_config(sirfport->rx_dma_chan, &slv_cfg); in sirfsoc_uart_probe()
1407 sirfport->tx_dma_chan = dma_request_slave_channel(port->dev, "tx"); in sirfsoc_uart_probe()
1408 if (sirfport->tx_dma_chan) in sirfsoc_uart_probe()
1409 dmaengine_slave_config(sirfport->tx_dma_chan, &tx_slv_cfg); in sirfsoc_uart_probe()
1410 if (sirfport->rx_dma_chan) { in sirfsoc_uart_probe()
1411 hrtimer_init(&sirfport->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in sirfsoc_uart_probe()
1412 sirfport->hrt.function = sirfsoc_uart_rx_dma_hrtimer_callback; in sirfsoc_uart_probe()
1413 sirfport->is_hrt_enabled = false; in sirfsoc_uart_probe()
1418 dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE, in sirfsoc_uart_probe()
1419 sirfport->rx_dma_items.xmit.buf, in sirfsoc_uart_probe()
1420 sirfport->rx_dma_items.dma_addr); in sirfsoc_uart_probe()
1421 dma_release_channel(sirfport->rx_dma_chan); in sirfsoc_uart_probe()
1429 struct uart_port *port = &sirfport->port; in sirfsoc_uart_remove()
1431 if (sirfport->rx_dma_chan) { in sirfsoc_uart_remove()
1432 dmaengine_terminate_all(sirfport->rx_dma_chan); in sirfsoc_uart_remove()
1433 dma_release_channel(sirfport->rx_dma_chan); in sirfsoc_uart_remove()
1434 dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE, in sirfsoc_uart_remove()
1435 sirfport->rx_dma_items.xmit.buf, in sirfsoc_uart_remove()
1436 sirfport->rx_dma_items.dma_addr); in sirfsoc_uart_remove()
1438 if (sirfport->tx_dma_chan) { in sirfsoc_uart_remove()
1439 dmaengine_terminate_all(sirfport->tx_dma_chan); in sirfsoc_uart_remove()
1440 dma_release_channel(sirfport->tx_dma_chan); in sirfsoc_uart_remove()
1450 struct uart_port *port = &sirfport->port; in sirfsoc_uart_suspend()
1458 struct uart_port *port = &sirfport->port; in sirfsoc_uart_resume()