Home
last modified time | relevance | path

Searched +full:cs +full:- +full:extra +full:- +full:delay (Results 1 – 25 of 83) sorted by relevance

1234

/linux-6.8/Documentation/devicetree/bindings/memory-controllers/
Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
[all …]
/linux-6.8/include/linux/platform_data/
Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
78 u32 t_ceasu; /* address setup to CS valid */
94 u32 t_ce; /* access time from CS asertion */
96 u32 t_cez_r; /* read CS deassertion to high Z */
97 u32 t_cez_w; /* write CS deassertion to high Z */
105 u32 t_bacc; /* burst access valid clock to output delay */
[all …]
/linux-6.8/drivers/memory/
Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
32 #include <linux/omap-gpmc.h>
36 #include <linux/platform_data/mtd-nand-omap2.h>
38 #define DEVICE_NAME "omap-gpmc"
206 /* Structure to save gpmc cs context */
257 /* Define chip-selects as reserved by default until probe completes */
277 void gpmc_cs_write_reg(int cs, int idx, u32 val) in gpmc_cs_write_reg() argument
281 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; in gpmc_cs_write_reg()
[all …]
/linux-6.8/include/linux/spi/
Dspi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later
23 /* Max no. of CS supported per spi device */
36 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
42 * struct spi_statistics - statistics for spi transfers
43 * @syncp: seqcount to protect members in this struct for per-cpu update
44 * on 32-bit systems
46 * @messages: number of spi-messages handled
95 u64_stats_update_begin(&__lstats->syncp); \
96 u64_stats_add(&__lstats->field, count); \
97 u64_stats_update_end(&__lstats->syncp); \
[all …]
/linux-6.8/net/ipv4/
Dtcp_vegas.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * IEEE Journal on Selected Areas in Communication, 13(8):1465--1480,
10 * ftp://ftp.cs.arizona.edu/xkernel/Papers/jsac.ps
12 * See http://www.cs.arizona.edu/xkernel/ for their implementation.
17 * using fine-grained timers, NewReno, and FACK.
19 * only every-other RTT during slow start, we increase during
29 * o When the sender re-starts from idle, it waits until it has
55 /* There are several situations when we must "re-start" Vegas:
65 * stale info -- both the saved cwnd and congestion feedback are
77 vegas->doing_vegas_now = 1; in vegas_enable()
[all …]
/linux-6.8/drivers/spi/
Dspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk/clk-conf.h>
10 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
35 #include <linux/spi/spi-mem.h>
51 spi_controller_put(spi->controller); in spidev_release()
52 kfree(spi->driver_override); in spidev_release()
53 free_percpu(spi->pcpu_statistics); in spidev_release()
63 len = acpi_device_modalias(dev, buf, PAGE_SIZE - 1); in modalias_show()
64 if (len != -ENODEV) in modalias_show()
[all …]
Dspi-mt7621.c1 // SPDX-License-Identifier: GPL-2.0
3 // spi-mt7621.c -- MediaTek MT7621 SPI controller driver
6 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
7 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
9 // Some parts are based on spi-orion.c:
11 // Copyright (C) 2007-2008 Marvell Ltd.
14 #include <linux/delay.h>
23 #define DRIVER_NAME "spi-mt7621"
65 return spi_controller_get_devdata(spi->controller); in spidev_to_mt7621_spi()
70 return ioread32(rs->base + reg); in mt7621_spi_read()
[all …]
Dspi-imx.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
8 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
26 #include <linux/dma/imx-dma.h>
133 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
138 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
143 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
148 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
154 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
[all …]
Dspi-fsl-lpspi.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
22 #include <linux/dma/imx-dma.h>
34 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
125 { .compatible = "fsl,imx7ulp-spi", },
133 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
135 if (fsl_lpspi->rx_buf) { \
136 *(type *)fsl_lpspi->rx_buf = val; \
137 fsl_lpspi->rx_buf += sizeof(type); \
[all …]
/linux-6.8/drivers/mtd/nand/raw/
Dpl35x-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/delay.h>
31 #define PL35X_NANDC_DRIVER_NAME "pl35x-nand-controller"
119 unsigned int cs; member
126 * struct pl35x_nandc - NAND flash controller driver structure
133 * @assigned_cs: List of assigned CS
162 if (section >= chip->ecc.steps) in pl35x_ecc_ooblayout16_ecc()
163 return -ERANGE; in pl35x_ecc_ooblayout16_ecc()
165 oobregion->offset = (section * chip->ecc.bytes); in pl35x_ecc_ooblayout16_ecc()
166 oobregion->length = chip->ecc.bytes; in pl35x_ecc_ooblayout16_ecc()
[all …]
Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
33 * ECC) sections and potentially an extra one to deal with
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
45 * -------------------------------------------
[all …]
Darasan-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
114 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
124 * struct anfc_op - Defines how to execute an operation
150 * struct anand - Defines the NAND chip related information
153 * @rb: Ready-busy line
157 * @timings: NV-DDR specific timings to use
167 * @cs_idx: Array of chip-select for this device, values are indexes
[all …]
Dsunxi_nand.c1 // SPDX-License-Identifier: GPL-2.0+
6 * https://github.com/yuq/sunxi-nfc-mtd
9 * https://github.com/hno/Allwinner-Info
16 #include <linux/dma-mapping.h>
26 #include <linux/delay.h>
70 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
107 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
161 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
163 * @cs: the NAND CS id used to communicate with a NAND Chip
164 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC
[all …]
/linux-6.8/drivers/gpu/drm/i915/gt/
Dintel_migrate.c1 // SPDX-License-Identifier: MIT
19 #define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
33 GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS); in engine_supports_migration()
48 vm->insert_page(vm, 0, d->offset, in xehpsdv_toggle_pdes()
49 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehpsdv_toggle_pdes()
51 GEM_BUG_ON(!pt->is_compact); in xehpsdv_toggle_pdes()
52 d->offset += SZ_2M; in xehpsdv_toggle_pdes()
68 vm->insert_page(vm, px_dma(pt), d->offset, in xehpsdv_insert_pte()
69 i915_gem_get_pat_index(vm->i915, I915_CACHE_NONE), in xehpsdv_insert_pte()
71 d->offset += SZ_64K; in xehpsdv_insert_pte()
[all …]
Dintel_ring_submission.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2008-2021 Intel Corporation
31 * set-context and then emitting the batch.
41 if (engine->class == RENDER_CLASS) { in set_hwstam()
42 if (GRAPHICS_VER(engine->i915) >= 6) in set_hwstam()
56 if (GRAPHICS_VER(engine->i915) >= 4) in set_hws_pga()
59 intel_uncore_write(engine->uncore, HWS_PGA, addr); in set_hws_pga()
64 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
67 return sg_page(obj->mm.pages->sgl); in status_page()
84 if (GRAPHICS_VER(engine->i915) == 7) { in set_hwsp()
[all …]
Dintel_execlists_submission.c1 // SPDX-License-Identifier: MIT
19 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
20 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
26 * rings, the engine cs shifts to a new "ring buffer" with every context
37 * - One global default context.
38 * - One local default context for each opened fd.
39 * - One local extra context for each context create ioctl call.
41 * Now that ringbuffers belong per-context (and not per-engine, like before)
45 * - One ringbuffer per-engine inside each context.
46 * - One backing object per-engine inside each context.
[all …]
Dintel_engine_cs.c1 // SPDX-License-Identifier: MIT
40 * on HSW) - so the final size, including the extra state required for the
260 * intel_engine_context_size() - return the size of the context for an engine
275 struct intel_uncore *uncore = gt->uncore; in intel_engine_context_size()
284 switch (GRAPHICS_VER(gt->i915)) { in intel_engine_context_size()
286 MISSING_CASE(GRAPHICS_VER(gt->i915)); in intel_engine_context_size()
296 if (IS_HASWELL(gt->i915)) in intel_engine_context_size()
320 GRAPHICS_VER(gt->i915), cxt_size * 64, in intel_engine_context_size()
321 cxt_size - 1); in intel_engine_context_size()
337 if (GRAPHICS_VER(gt->i915) < 8) in intel_engine_context_size()
[all …]
/linux-6.8/include/linux/mtd/
Drawnand.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
75 #define NAND_CMD_NONE -1
84 #define NAND_DATA_IFACE_CHECK_ONLY -1
98 * ecc.correct() returns -EBADMSG.
124 * Chip requires ready check on read (for auto-incremented sequential read).
142 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
174 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
175 * on the default ->cmdfunc() implementation, you may want to let the core
176 * handle the tCCS delay which is required when a column change (RNDIN or
[all …]
/linux-6.8/drivers/infiniband/hw/qib/
Dqib_iba6120.c2 * Copyright (c) 2013 - 2017 Intel Corporation. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
42 #include <linux/delay.h>
54 * This file contains all the chip-specific register information and
55 * access functions for the Intel Intel_IB PCI-Express chip.
59 /* KREG_IDX uses machine-generated #defines */
62 /* Use defines to tie machine-generated names to lower-case names */
115 #define CREG_IDX(regname) ((QIB_6120_##regname##_OFFS - \
237 * DDR when faking DDR negotiations with non-IBTA switches.
[all …]
/linux-6.8/drivers/iio/adc/
Dad7923.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright 2012 CS Systemes d'Information
17 #include <linux/delay.h>
47 #define EXTRACT(val, dec, bits) (((val) >> (dec)) & ((1 << (bits)) - 1))
64 * Length = 8 channels + 4 extra for 8 byte timestamp
97 .shift = 12 - (bits), \
172 for_each_set_bit(i, active_scan_mask, indio_dev->num_channels - 1) { in ad7923_update_scan_mode()
175 st->settings; in ad7923_update_scan_mode()
177 st->tx_buf[len++] = cpu_to_be16(cmd); in ad7923_update_scan_mode()
180 st->ring_xfer[0].tx_buf = &st->tx_buf[0]; in ad7923_update_scan_mode()
[all …]
/linux-6.8/drivers/staging/fbtft/
Dfbtft-core.c1 // SPDX-License-Identifier: GPL-2.0+
21 #include <linux/delay.h>
41 gpiod_set_value(par->gpio.dc, dc); in fbtft_write_buf_dc()
43 ret = par->fbtftops.write(par, buf, len); in fbtft_write_buf_dc()
45 dev_err(par->info->device, in fbtft_write_buf_dc()
64 512 - text_len, false); in fbtft_dbg_hex()
77 struct device *dev = par->info->device; in fbtft_request_one_gpio()
95 ret = fbtft_request_one_gpio(par, "reset", 0, &par->gpio.reset); in fbtft_request_gpios()
98 ret = fbtft_request_one_gpio(par, "dc", 0, &par->gpio.dc); in fbtft_request_gpios()
101 ret = fbtft_request_one_gpio(par, "rd", 0, &par->gpio.rd); in fbtft_request_gpios()
[all …]
/linux-6.8/include/linux/iio/imu/
Dadis.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
26 * struct adis_timeouts - ADIS chip variant timeouts
27 * @reset_ms - Wait time after rst pin goes inactive
28 * @sw_reset_ms - Wait time after sw reset command
29 * @self_test_ms - Wait time after self test command
38 * struct adis_data - ADIS chip variant specific data
39 * @read_delay: SPI delay for read operations in us
40 * @write_delay: SPI delay for write operations in us
41 * @cs_change_delay: SPI delay between CS changes in us
[all …]
/linux-6.8/Documentation/spi/
Dspi-summary.rst5 02-Feb-2012
8 ------------
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
32 - SPI may be used for request/response style device protocols, as with
35 - It may also be used to stream data in either direction (half duplex),
38 - Some devices may use eight bit words. Others may use different word
39 lengths, such as streams of 12-bit or 20-bit digital samples.
41 - Words are usually sent with their most significant bit (MSB) first,
44 - Sometimes SPI is used to daisy-chain devices, like shift registers.
51 SPI is only one of the names used by such four-wire protocols, and
[all …]
/linux-6.8/arch/arm/mach-sa1100/
Dgeneric.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/generic.c
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
23 #include <linux/irqchip/irq-sa11x0.h>
75 * Default power-off for SA1100
81 /* disable internal oscillator, float CS lines */ in sa1100_power_off()
83 /* enable wake-up on GPIO0 (Assabet...) */ in sa1100_power_off()
102 /* Use on-chip reset capability */ in sa11x0_restart()
110 dev->dev.platform_data = data; in sa11x0_register_device()
[all …]
/linux-6.8/kernel/cgroup/
Dcpuset.c7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
28 #include <linux/delay.h>
54 * node binding, add this key to provide a quick low-cost judgment
102 * The user-configured masks can only be changed by writing to
116 * The user-configured masks are always the same with effective masks.
119 /* user-configured CPUs and Memory Nodes allow to tasks */
[all …]

1234