Lines Matching +full:cs +full:- +full:extra +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0
3 // spi-mt7621.c -- MediaTek MT7621 SPI controller driver
6 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
7 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
9 // Some parts are based on spi-orion.c:
11 // Copyright (C) 2007-2008 Marvell Ltd.
14 #include <linux/delay.h>
23 #define DRIVER_NAME "spi-mt7621"
65 return spi_controller_get_devdata(spi->controller); in spidev_to_mt7621_spi()
70 return ioread32(rs->base + reg); in mt7621_spi_read()
75 iowrite32(val, rs->base + reg); in mt7621_spi_write()
81 int cs = spi_get_chipselect(spi, 0); in mt7621_spi_set_cs() local
87 * full-duplex (only half-duplex really works on this chip in mt7621_spi_set_cs()
95 rs->pending_write = 0; in mt7621_spi_set_cs()
98 polar = BIT(cs); in mt7621_spi_set_cs()
108 dev_dbg(&spi->dev, "speed:%u\n", speed); in mt7621_spi_prepare()
110 rate = DIV_ROUND_UP(rs->sys_freq, speed); in mt7621_spi_prepare()
111 dev_dbg(&spi->dev, "rate-1:%u\n", rate); in mt7621_spi_prepare()
114 return -EINVAL; in mt7621_spi_prepare()
121 reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT; in mt7621_spi_prepare()
122 rs->speed = speed; in mt7621_spi_prepare()
125 if (spi->mode & SPI_LSB_FIRST) in mt7621_spi_prepare()
154 return -ETIMEDOUT; in mt7621_spi_wait_till_ready()
163 * Combine with any pending write, and perform one or more half-duplex in mt7621_spi_read_half_duplex()
167 tx_len = rs->pending_write; in mt7621_spi_read_half_duplex()
168 rs->pending_write = 0; in mt7621_spi_read_half_duplex()
176 val |= (tx_len - 4) * 8; in mt7621_spi_read_half_duplex()
195 rx_len -= i; in mt7621_spi_read_half_duplex()
207 int len = rs->pending_write; in mt7621_spi_write_half_duplex()
213 val <<= (4 - len) * 8; in mt7621_spi_write_half_duplex()
220 rs->pending_write = len; in mt7621_spi_write_half_duplex()
229 /* The byte-order of the opcode is weird! */ in mt7621_spi_write_half_duplex()
231 mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val); in mt7621_spi_write_half_duplex()
234 tx_len -= 1; in mt7621_spi_write_half_duplex()
240 val >>= (4 - len) * 8; in mt7621_spi_write_half_duplex()
245 rs->pending_write = len; in mt7621_spi_write_half_duplex()
252 struct spi_device *spi = m->spi; in mt7621_spi_transfer_one_message()
253 unsigned int speed = spi->max_speed_hz; in mt7621_spi_transfer_one_message()
259 list_for_each_entry(t, &m->transfers, transfer_list) in mt7621_spi_transfer_one_message()
260 if (t->speed_hz < speed) in mt7621_spi_transfer_one_message()
261 speed = t->speed_hz; in mt7621_spi_transfer_one_message()
264 status = -EIO; in mt7621_spi_transfer_one_message()
268 /* Assert CS */ in mt7621_spi_transfer_one_message()
271 m->actual_length = 0; in mt7621_spi_transfer_one_message()
272 list_for_each_entry(t, &m->transfers, transfer_list) { in mt7621_spi_transfer_one_message()
273 if ((t->rx_buf) && (t->tx_buf)) { in mt7621_spi_transfer_one_message()
275 * This controller will shift some extra data out in mt7621_spi_transfer_one_message()
277 * (cmd_bit_cnt == 0). So the claimed full-duplex in mt7621_spi_transfer_one_message()
281 status = -EIO; in mt7621_spi_transfer_one_message()
283 } else if (t->rx_buf) { in mt7621_spi_transfer_one_message()
284 mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf); in mt7621_spi_transfer_one_message()
285 } else if (t->tx_buf) { in mt7621_spi_transfer_one_message()
286 mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf); in mt7621_spi_transfer_one_message()
288 m->actual_length += t->len; in mt7621_spi_transfer_one_message()
291 /* Flush data and deassert CS */ in mt7621_spi_transfer_one_message()
296 m->status = status; in mt7621_spi_transfer_one_message()
306 if ((spi->max_speed_hz == 0) || in mt7621_spi_setup()
307 (spi->max_speed_hz > (rs->sys_freq / 2))) in mt7621_spi_setup()
308 spi->max_speed_hz = rs->sys_freq / 2; in mt7621_spi_setup()
310 if (spi->max_speed_hz < (rs->sys_freq / 4097)) { in mt7621_spi_setup()
311 dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n", in mt7621_spi_setup()
312 spi->max_speed_hz); in mt7621_spi_setup()
313 return -EINVAL; in mt7621_spi_setup()
320 { .compatible = "ralink,mt7621-spi" },
334 match = of_match_device(mt7621_spi_match, &pdev->dev); in mt7621_spi_probe()
336 return -EINVAL; in mt7621_spi_probe()
342 clk = devm_clk_get_enabled(&pdev->dev, NULL); in mt7621_spi_probe()
344 return dev_err_probe(&pdev->dev, PTR_ERR(clk), in mt7621_spi_probe()
347 host = devm_spi_alloc_host(&pdev->dev, sizeof(*rs)); in mt7621_spi_probe()
349 dev_info(&pdev->dev, "host allocation failed\n"); in mt7621_spi_probe()
350 return -ENOMEM; in mt7621_spi_probe()
353 host->mode_bits = SPI_LSB_FIRST; in mt7621_spi_probe()
354 host->flags = SPI_CONTROLLER_HALF_DUPLEX; in mt7621_spi_probe()
355 host->setup = mt7621_spi_setup; in mt7621_spi_probe()
356 host->transfer_one_message = mt7621_spi_transfer_one_message; in mt7621_spi_probe()
357 host->bits_per_word_mask = SPI_BPW_MASK(8); in mt7621_spi_probe()
358 host->dev.of_node = pdev->dev.of_node; in mt7621_spi_probe()
359 host->num_chipselect = 2; in mt7621_spi_probe()
361 dev_set_drvdata(&pdev->dev, host); in mt7621_spi_probe()
364 rs->base = base; in mt7621_spi_probe()
365 rs->host = host; in mt7621_spi_probe()
366 rs->sys_freq = clk_get_rate(clk); in mt7621_spi_probe()
367 rs->pending_write = 0; in mt7621_spi_probe()
368 dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq); in mt7621_spi_probe()
370 ret = device_reset(&pdev->dev); in mt7621_spi_probe()
372 dev_err(&pdev->dev, "SPI reset failed!\n"); in mt7621_spi_probe()
376 return devm_spi_register_controller(&pdev->dev, host); in mt7621_spi_probe()