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Searched +full:coresight +full:- +full:tmc (Results 1 – 25 of 39) sorted by relevance

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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-coresight-devices-tmc1 What: /sys/bus/coresight/devices/<memory_map>.tmc/trigger_cntr
10 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rsz
14 Description: (Read) Defines the size, in 32-bit words, of the local RAM buffer.
17 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/sts
21 Description: (Read) Shows the value held by the TMC status register. The value
24 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rrp
28 Description: (Read) Shows the value held by the TMC RAM Read Pointer register
33 What: /sys/bus/coresight/devices/<memory_map>.tmc/mgmt/rwp
37 Description: (Read) Shows the value held by the TMC RAM Write Pointer register
39 the CoreSight bus into the Trace RAM. The value is read directly
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/linux/drivers/hwtracing/coresight/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for CoreSight drivers.
7 subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
8 subdir-ccflags-y += -Wmissing-declarations
9 subdir-ccflags-y += -Wmissing-format-attribute
10 subdir-ccflags-y += -Wmissing-prototypes
11 subdir-ccflags-y += -Wold-style-definition
12 subdir-ccflags-y += -Wmissing-include-dirs
13 subdir-ccflags-y += -Wno-sign-compare
15 $(call cc-option, -Wrestrict) \
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Coresight configuration
5 menuconfig CORESIGHT config
6 tristate "CoreSight Tracing Support"
13 This framework provides a kernel interface for the CoreSight debug
15 a topological view of the CoreSight components based on a DT
20 module will be called coresight.
22 if CORESIGHT
24 tristate "CoreSight Link and Sink drivers"
26 This enables support for CoreSight link and sink drivers that are
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H A Dcoresight-tmc-core.c1 // SPDX-License-Identifier: GPL-2.0
4 * Description: CoreSight Trace Memory Controller driver
22 #include <linux/dma-mapping.h>
27 #include <linux/coresight.h>
31 #include "coresight-priv.h"
32 #include "coresight-tmc.h"
40 struct coresight_device *csdev = drvdata->csdev; in tmc_wait_for_tmcready()
41 struct csdev_access *csa = &csdev->access; in tmc_wait_for_tmcready()
45 dev_err(&csdev->dev, in tmc_wait_for_tmcready()
46 "timeout while waiting for TMC to be Ready\n"); in tmc_wait_for_tmcready()
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H A Dcoresight-ctcu-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
7 #include <linux/coresight.h>
19 #include "coresight-ctcu.h"
20 #include "coresight-priv.h"
24 #define ctcu_writel(drvdata, val, offset) __raw_writel((val), drvdata->base + offset)
25 #define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base + offset)
28 * The TMC Coresight Control Unit utilizes four ATID registers to control the data
29 * filter function based on the trace ID for each TMC ETR sink. The length of each
30 * ATID register is 32 bits. Therefore, an ETR device has a 128-bit long field
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H A Dcoresight-tmc.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/dma-mapping.h>
46 /* TMC_CTL - 0x020 */
48 /* TMC_STS - 0x00C */
54 * TMC_AXICTL - 0x110
56 * TMC AXICTL format for SoC-400
57 * Bits [0-1] : ProtCtrlBit0-1
58 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE)
61 * Bits [8-11] : WrBurstLen
62 * Bits [12-31] : Reserved.
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H A Dcoresight-tmc-etr.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/coresight.h>
9 #include <linux/dma-mapping.h>
17 #include "coresight-catu.h"
18 #include "coresight-etm-perf.h"
19 #include "coresight-priv.h"
20 #include "coresight-tmc.h"
37 * etr_perf_buffer - Perf buffer used for ETR
38 * @drvdata - The ETR drvdaga this buffer has been allocated for.
39 * @etr_buf - Actual buffer used by the ETR
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H A Dcoresight-catu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Coresight Address Translation Unit support
13 #include <linux/dma-mapping.h>
19 #include "coresight-catu.h"
20 #include "coresight-priv.h"
21 #include "coresight-tmc.h"
24 dev_get_drvdata(csdev->dev.parent)
45 * ------------------------------------
46 * | Address [63-12] | SBZ | V|
47 * ------------------------------------
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/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-tmc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm CoreSight Trace Memory Controller
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
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H A Dqcom,coresight-ctcu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/qcom,coresight-ctcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CoreSight TMC Control Unit
10 - Yuanfang Zhang <quic_yuanfang@quicinc.com>
11 - Mao Jinlong <quic_jinlmao@quicinc.com>
12 - Jie Gan <quic_jiegan@quicinc.com>
15 The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB),
20 The Coresight TMC Control unit controls various Coresight behaviors.
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H A Dqcom,coresight-remote-etm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/qcom,coresight-remote-etm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Coresight Remote ETM(Embedded Trace Macrocell)
10 - Jinlong Mao <quic_jinlmao@quicinc.com>
11 - Tao Zhang <quic_taozha@quicinc.com>
14 Support for ETM trace collection on remote processor using coresight
17 via coresight TMC sinks.
21 const: qcom,coresight-remote-etm
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H A Darm,coresight-catu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Coresight Address Translation Unit (CATU)
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
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H A Dqcom,coresight-tpda.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/qcom,coresight-tpda.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Trace, Profiling and Diagnostics Aggregator - TPDA
15 task for free-flowing data from TPDM (i.e. CMB and DSB data set flows).
19 TPDM source to TMC sink. TPDM can directly connect to TPDA's inport or
23 Enable coresight sink first.
25 echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
26 echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source
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/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3660-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * dtsi for Hisilicon Hi3660 Coresight
6 * Copyright (C) 2016-2018 HiSilicon Ltd.
15 compatible = "arm,coresight-etm4x", "arm,primecell";
18 clock-names = "apb_pclk";
20 arm,coresight-loses-context-with-cpu;
22 out-ports {
25 remote-endpoint =
33 compatible = "arm,coresight-etm4x", "arm,primecell";
36 clock-names = "apb_pclk";
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H A Dhi6220-coresight.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * dtsi file for Hisilicon Hi6220 coresight
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
17 clock-names = "apb_pclk";
19 out-ports {
22 remote-endpoint =
28 in-ports {
31 remote-endpoint =
39 compatible = "arm,coresight-tmc", "arm,primecell";
42 clock-names = "apb_pclk";
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/linux/arch/arm64/boot/dts/sprd/
H A Dsc9863a.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <0>;
17 cpu-map {
48 compatible = "arm,cortex-a55";
50 enable-method = "psci";
51 cpu-idle-states = <&CORE_PD>;
56 compatible = "arm,cortex-a55";
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H A Dsc9860.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
55 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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H A Dsc9836.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #address-cells = <2>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
22 enable-method = "psci";
27 compatible = "arm,cortex-a53";
29 enable-method = "psci";
34 compatible = "arm,cortex-a53";
36 enable-method = "psci";
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H A Dums512.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
51 compatible = "arm,cortex-a55";
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/linux/arch/arm64/boot/dts/arm/
H A Djuno-cs-r1r2.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
8 clock-names = "apb_pclk";
9 power-domains = <&scpi_devpd 0>;
10 out-ports {
13 remote-endpoint = <&etf1_in_port>;
17 in-ports {
27 compatible = "arm,coresight-tmc", "arm,primecell";
31 clock-names = "apb_pclk";
32 power-domains = <&scpi_devpd 0>;
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H A Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 #address-cells = <1>;
14 #size-cells = <1>;
18 frame-number = <1>;
30 #mbox-cells = <1>;
32 clock-names = "apb_pclk";
36 compatible = "arm,mmu-400", "arm,smmu-v1";
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/linux/Documentation/trace/coresight/
H A Dpanic.rst2 Using Coresight for Kernel panic and Watchdog reset
6 ------------
7 This documentation is about using Linux coresight trace support to
10 Coresight trace during Kernel panic
11 -----------------------------------
12 From the coresight driver point of view, addressing the kernel panic
17 relevant coresight nodes.
19 b. Support for stopping coresight blocks at the time of panic
27 A new optional device tree property "memory-region" is added to the
28 Coresight TMC device nodes, that would give the base address and size of trace
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/linux/arch/arm64/boot/dts/qcom/
H A Dqcs615.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qcs615-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/interconnect/qcom,icc.h>
10 #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
13 #include <dt-bindings/power/qcom,rpmhpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
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H A Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm8916.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
13 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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