Lines Matching +full:coresight +full:- +full:tmc
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qcs615-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/interconnect/qcom,icc.h>
10 #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
13 #include <dt-bindings/power/qcom,rpmhpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <2>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a55";
29 enable-method = "psci";
30 power-domains = <&cpu_pd0>;
31 power-domain-names = "psci";
32 capacity-dmips-mhz = <1024>;
33 dynamic-power-coefficient = <100>;
34 next-level-cache = <&l2_0>;
35 #cooling-cells = <2>;
37 l2_0: l2-cache {
39 cache-level = <2>;
40 cache-unified;
41 next-level-cache = <&l3_0>;
47 compatible = "arm,cortex-a55";
49 enable-method = "psci";
50 power-domains = <&cpu_pd1>;
51 power-domain-names = "psci";
52 capacity-dmips-mhz = <1024>;
53 dynamic-power-coefficient = <100>;
54 next-level-cache = <&l2_100>;
56 l2_100: l2-cache {
58 cache-level = <2>;
59 cache-unified;
60 next-level-cache = <&l3_0>;
66 compatible = "arm,cortex-a55";
68 enable-method = "psci";
69 power-domains = <&cpu_pd2>;
70 power-domain-names = "psci";
71 capacity-dmips-mhz = <1024>;
72 dynamic-power-coefficient = <100>;
73 next-level-cache = <&l2_200>;
75 l2_200: l2-cache {
77 cache-level = <2>;
78 cache-unified;
79 next-level-cache = <&l3_0>;
85 compatible = "arm,cortex-a55";
87 enable-method = "psci";
88 power-domains = <&cpu_pd3>;
89 power-domain-names = "psci";
90 capacity-dmips-mhz = <1024>;
91 dynamic-power-coefficient = <100>;
92 next-level-cache = <&l2_300>;
94 l2_300: l2-cache {
96 cache-level = <2>;
97 cache-unified;
98 next-level-cache = <&l3_0>;
104 compatible = "arm,cortex-a55";
106 enable-method = "psci";
107 power-domains = <&cpu_pd4>;
108 power-domain-names = "psci";
109 capacity-dmips-mhz = <1024>;
110 dynamic-power-coefficient = <100>;
111 next-level-cache = <&l2_400>;
113 l2_400: l2-cache {
115 cache-level = <2>;
116 cache-unified;
117 next-level-cache = <&l3_0>;
123 compatible = "arm,cortex-a55";
125 enable-method = "psci";
126 power-domains = <&cpu_pd5>;
127 power-domain-names = "psci";
128 capacity-dmips-mhz = <1024>;
129 dynamic-power-coefficient = <100>;
130 next-level-cache = <&l2_500>;
132 l2_500: l2-cache {
134 cache-level = <2>;
135 cache-unified;
136 next-level-cache = <&l3_0>;
142 compatible = "arm,cortex-a76";
144 enable-method = "psci";
145 power-domains = <&cpu_pd6>;
146 power-domain-names = "psci";
147 capacity-dmips-mhz = <1740>;
148 dynamic-power-coefficient = <404>;
149 next-level-cache = <&l2_600>;
150 #cooling-cells = <2>;
152 l2_600: l2-cache {
154 cache-level = <2>;
155 cache-unified;
156 next-level-cache = <&l3_0>;
162 compatible = "arm,cortex-a76";
164 enable-method = "psci";
165 power-domains = <&cpu_pd7>;
166 power-domain-names = "psci";
167 capacity-dmips-mhz = <1740>;
168 dynamic-power-coefficient = <404>;
169 next-level-cache = <&l2_700>;
171 l2_700: l2-cache {
173 cache-level = <2>;
174 cache-unified;
175 next-level-cache = <&l3_0>;
179 cpu-map {
215 l3_0: l3-cache {
217 cache-level = <3>;
218 cache-unified;
222 dummy_eud: dummy-sink {
223 compatible = "arm,coresight-dummy-sink";
225 in-ports {
228 remote-endpoint = <&replicator_swao_out1>;
234 idle-states {
235 entry-method = "psci";
237 little_cpu_sleep_0: cpu-sleep-0-0 {
238 compatible = "arm,idle-state";
239 idle-state-name = "silver-power-collapse";
240 arm,psci-suspend-param = <0x40000003>;
241 entry-latency-us = <549>;
242 exit-latency-us = <901>;
243 min-residency-us = <1774>;
244 local-timer-stop;
247 little_cpu_sleep_1: cpu-sleep-0-1 {
248 compatible = "arm,idle-state";
249 idle-state-name = "silver-rail-power-collapse";
250 arm,psci-suspend-param = <0x40000004>;
251 entry-latency-us = <702>;
252 exit-latency-us = <915>;
253 min-residency-us = <4001>;
254 local-timer-stop;
257 big_cpu_sleep_0: cpu-sleep-1-0 {
258 compatible = "arm,idle-state";
259 idle-state-name = "gold-power-collapse";
260 arm,psci-suspend-param = <0x40000003>;
261 entry-latency-us = <523>;
262 exit-latency-us = <1244>;
263 min-residency-us = <2207>;
264 local-timer-stop;
267 big_cpu_sleep_1: cpu-sleep-1-1 {
268 compatible = "arm,idle-state";
269 idle-state-name = "gold-rail-power-collapse";
270 arm,psci-suspend-param = <0x40000004>;
271 entry-latency-us = <526>;
272 exit-latency-us = <1854>;
273 min-residency-us = <5555>;
274 local-timer-stop;
278 domain-idle-states {
279 cluster_sleep_0: cluster-sleep-0 {
280 compatible = "domain-idle-state";
281 arm,psci-suspend-param = <0x41000044>;
282 entry-latency-us = <2752>;
283 exit-latency-us = <3048>;
284 min-residency-us = <6118>;
287 cluster_sleep_1: cluster-sleep-1 {
288 compatible = "domain-idle-state";
289 arm,psci-suspend-param = <0x41001344>;
290 entry-latency-us = <3263>;
291 exit-latency-us = <4562>;
292 min-residency-us = <8467>;
295 cluster_sleep_2: cluster-sleep-2 {
296 compatible = "domain-idle-state";
297 arm,psci-suspend-param = <0x4100b344>;
298 entry-latency-us = <3638>;
299 exit-latency-us = <6562>;
300 min-residency-us = <9826>;
312 compatible = "qcom,scm-qcs615", "qcom,scm";
313 qcom,dload-mode = <&tcsr 0x13000>;
317 camnoc_virt: interconnect-0 {
318 compatible = "qcom,qcs615-camnoc-virt";
319 #interconnect-cells = <2>;
320 qcom,bcm-voters = <&apps_bcm_voter>;
323 ipa_virt: interconnect-1 {
324 compatible = "qcom,qcs615-ipa-virt";
325 #interconnect-cells = <2>;
326 qcom,bcm-voters = <&apps_bcm_voter>;
329 mc_virt: interconnect-2 {
330 compatible = "qcom,qcs615-mc-virt";
331 #interconnect-cells = <2>;
332 qcom,bcm-voters = <&apps_bcm_voter>;
335 smp2p-adsp {
342 qcom,local-pid = <0>;
343 qcom,remote-pid = <2>;
345 adsp_smp2p_out: master-kernel {
346 qcom,entry-name = "master-kernel";
347 #qcom,smem-state-cells = <1>;
350 adsp_smp2p_in: slave-kernel {
351 qcom,entry-name = "slave-kernel";
352 interrupt-controller;
353 #interrupt-cells = <2>;
357 smp2p-cdsp {
363 qcom,local-pid = <0>;
364 qcom,remote-pid = <5>;
366 cdsp_smp2p_out: master-kernel {
367 qcom,entry-name = "master-kernel";
368 #qcom,smem-state-cells = <1>;
371 cdsp_smp2p_in: slave-kernel {
372 qcom,entry-name = "slave-kernel";
373 interrupt-controller;
374 #interrupt-cells = <2>;
379 qup_opp_table: opp-table-qup {
380 compatible = "operating-points-v2";
381 opp-shared;
383 opp-75000000 {
384 opp-hz = /bits/ 64 <75000000>;
385 required-opps = <&rpmhpd_opp_low_svs>;
388 opp-100000000 {
389 opp-hz = /bits/ 64 <100000000>;
390 required-opps = <&rpmhpd_opp_svs>;
393 opp-128000000 {
394 opp-hz = /bits/ 64 <128000000>;
395 required-opps = <&rpmhpd_opp_nom>;
400 compatible = "arm,psci-1.0";
403 cpu_pd0: power-domain-cpu0 {
404 #power-domain-cells = <0>;
405 power-domains = <&cluster_pd>;
406 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
409 cpu_pd1: power-domain-cpu1 {
410 #power-domain-cells = <0>;
411 power-domains = <&cluster_pd>;
412 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
415 cpu_pd2: power-domain-cpu2 {
416 #power-domain-cells = <0>;
417 power-domains = <&cluster_pd>;
418 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
421 cpu_pd3: power-domain-cpu3 {
422 #power-domain-cells = <0>;
423 power-domains = <&cluster_pd>;
424 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
427 cpu_pd4: power-domain-cpu4 {
428 #power-domain-cells = <0>;
429 power-domains = <&cluster_pd>;
430 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
433 cpu_pd5: power-domain-cpu5 {
434 #power-domain-cells = <0>;
435 power-domains = <&cluster_pd>;
436 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
439 cpu_pd6: power-domain-cpu6 {
440 #power-domain-cells = <0>;
441 power-domains = <&cluster_pd>;
442 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
445 cpu_pd7: power-domain-cpu7 {
446 #power-domain-cells = <0>;
447 power-domains = <&cluster_pd>;
448 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
451 cluster_pd: power-domain-cluster {
452 #power-domain-cells = <0>;
453 domain-idle-states = <&cluster_sleep_0
459 reserved-memory {
460 #address-cells = <2>;
461 #size-cells = <2>;
464 aop_cmd_db_mem: aop-cmd-db@85f20000 {
465 compatible = "qcom,cmd-db";
467 no-map;
473 no-map;
477 rproc_cdsp_mem: rproc-cdsp@93b00000 {
479 no-map;
482 rproc_adsp_mem: rproc-adsp@95900000 {
484 no-map;
489 compatible = "simple-bus";
491 dma-ranges = <0 0 0 0 0x10 0>;
492 #address-cells = <2>;
493 #size-cells = <2>;
495 gcc: clock-controller@100000 {
496 compatible = "qcom,qcs615-gcc";
499 #clock-cells = <1>;
500 #reset-cells = <1>;
501 #power-domain-cells = <1>;
505 compatible = "qcom,qcs615-qfprom", "qcom,qfprom";
507 #address-cells = <1>;
508 #size-cells = <1>;
510 qusb2_hstx_trim: hstx-trim@1f8 {
517 compatible = "qcom,qcs615-trng", "qcom,trng";
522 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
526 reg-names = "hc",
532 interrupt-names = "hc_irq",
539 clock-names = "iface",
546 power-domains = <&rpmhpd RPMHPD_CX>;
547 operating-points-v2 = <&sdhc1_opp_table>;
553 interconnect-names = "sdhc-ddr",
554 "cpu-sdhc";
556 qcom,dll-config = <0x000f642c>;
557 qcom,ddr-config = <0x80040868>;
558 supports-cqe;
559 dma-coherent;
563 sdhc1_opp_table: opp-table {
564 compatible = "operating-points-v2";
566 opp-50000000 {
567 opp-hz = /bits/ 64 <50000000>;
568 required-opps = <&rpmhpd_opp_low_svs>;
571 opp-100000000 {
572 opp-hz = /bits/ 64 <100000000>;
573 required-opps = <&rpmhpd_opp_svs>;
576 opp-200000000 {
577 opp-hz = /bits/ 64 <200000000>;
578 required-opps = <&rpmhpd_opp_svs_l1>;
581 opp-384000000 {
582 opp-hz = /bits/ 64 <384000000>;
583 required-opps = <&rpmhpd_opp_nom>;
588 gpi_dma0: dma-controller@800000 {
589 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
591 #dma-cells = <3>;
600 dma-channels = <8>;
601 dma-channel-mask = <0xf>;
607 compatible = "qcom,geni-se-qup";
612 clock-names = "m-ahb",
613 "s-ahb";
615 #address-cells = <2>;
616 #size-cells = <2>;
620 compatible = "qcom,geni-debug-uart";
623 clock-names = "se";
624 pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>;
625 pinctrl-names = "default";
631 interconnect-names = "qup-core",
632 "qup-config";
633 power-domains = <&rpmhpd RPMHPD_CX>;
638 compatible = "qcom,geni-i2c";
640 #address-cells = <1>;
641 #size-cells = <0>;
644 clock-names = "se";
645 pinctrl-0 = <&qup_i2c1_data_clk>;
646 pinctrl-names = "default";
653 interconnect-names = "qup-core",
654 "qup-config",
655 "qup-memory";
656 power-domains = <&rpmhpd RPMHPD_CX>;
659 dma-names = "tx",
665 compatible = "qcom,geni-i2c";
667 #address-cells = <1>;
668 #size-cells = <0>;
671 clock-names = "se";
672 pinctrl-0 = <&qup_i2c2_data_clk>;
673 pinctrl-names = "default";
680 interconnect-names = "qup-core",
681 "qup-config",
682 "qup-memory";
683 power-domains = <&rpmhpd RPMHPD_CX>;
686 dma-names = "tx",
692 compatible = "qcom,geni-spi";
696 clock-names = "se";
697 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
698 pinctrl-names = "default";
703 interconnect-names = "qup-core",
704 "qup-config";
705 power-domains = <&rpmhpd RPMHPD_CX>;
708 dma-names = "tx",
710 #address-cells = <1>;
711 #size-cells = <0>;
716 compatible = "qcom,geni-uart";
720 clock-names = "se";
721 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>,
723 pinctrl-names = "default";
728 interconnect-names = "qup-core",
729 "qup-config";
730 power-domains = <&rpmhpd RPMHPD_CX>;
735 compatible = "qcom,geni-i2c";
737 #address-cells = <1>;
738 #size-cells = <0>;
741 clock-names = "se";
742 pinctrl-0 = <&qup_i2c3_data_clk>;
743 pinctrl-names = "default";
750 interconnect-names = "qup-core",
751 "qup-config",
752 "qup-memory";
753 power-domains = <&rpmhpd RPMHPD_CX>;
756 dma-names = "tx",
762 gpi_dma1: dma-controller@a00000 {
763 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma";
765 #dma-cells = <3>;
774 dma-channels = <8>;
775 dma-channel-mask = <0xf>;
781 compatible = "qcom,geni-se-qup";
786 clock-names = "m-ahb",
787 "s-ahb";
789 #address-cells = <2>;
790 #size-cells = <2>;
794 compatible = "qcom,geni-i2c";
797 clock-names = "se";
798 pinctrl-0 = <&qup_i2c4_data_clk>;
799 pinctrl-names = "default";
801 #address-cells = <1>;
802 #size-cells = <0>;
809 interconnect-names = "qup-core",
810 "qup-config",
811 "qup-memory";
812 power-domains = <&rpmhpd RPMHPD_CX>;
813 required-opps = <&rpmhpd_opp_low_svs>;
816 dma-names = "tx",
822 compatible = "qcom,geni-spi";
825 clock-names = "se";
826 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
827 pinctrl-names = "default";
829 #address-cells = <1>;
830 #size-cells = <0>;
835 interconnect-names = "qup-core",
836 "qup-config";
837 power-domains = <&rpmhpd RPMHPD_CX>;
838 operating-points-v2 = <&qup_opp_table>;
841 dma-names = "tx",
847 compatible = "qcom,geni-uart";
850 clock-names = "se";
851 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>,
853 pinctrl-names = "default";
859 interconnect-names = "qup-core",
860 "qup-config";
861 power-domains = <&rpmhpd RPMHPD_CX>;
862 operating-points-v2 = <&qup_opp_table>;
867 compatible = "qcom,geni-i2c";
870 clock-names = "se";
871 pinctrl-0 = <&qup_i2c5_data_clk>;
872 pinctrl-names = "default";
874 #address-cells = <1>;
875 #size-cells = <0>;
882 interconnect-names = "qup-core",
883 "qup-config",
884 "qup-memory";
885 power-domains = <&rpmhpd RPMHPD_CX>;
886 required-opps = <&rpmhpd_opp_low_svs>;
889 dma-names = "tx",
895 compatible = "qcom,geni-i2c";
898 clock-names = "se";
899 pinctrl-0 = <&qup_i2c6_data_clk>;
900 pinctrl-names = "default";
902 #address-cells = <1>;
903 #size-cells = <0>;
910 interconnect-names = "qup-core",
911 "qup-config",
912 "qup-memory";
913 power-domains = <&rpmhpd RPMHPD_CX>;
914 required-opps = <&rpmhpd_opp_low_svs>;
917 dma-names = "tx",
923 compatible = "qcom,geni-spi";
926 clock-names = "se";
927 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
928 pinctrl-names = "default";
930 #address-cells = <1>;
931 #size-cells = <0>;
936 interconnect-names = "qup-core",
937 "qup-config";
938 power-domains = <&rpmhpd RPMHPD_CX>;
939 operating-points-v2 = <&qup_opp_table>;
942 dma-names = "tx",
948 compatible = "qcom,geni-uart";
951 clock-names = "se";
952 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>,
954 pinctrl-names = "default";
960 interconnect-names = "qup-core",
961 "qup-config";
962 power-domains = <&rpmhpd RPMHPD_CX>;
963 operating-points-v2 = <&qup_opp_table>;
968 compatible = "qcom,geni-i2c";
971 clock-names = "se";
972 pinctrl-0 = <&qup_i2c7_data_clk>;
973 pinctrl-names = "default";
975 #address-cells = <1>;
976 #size-cells = <0>;
983 interconnect-names = "qup-core",
984 "qup-config",
985 "qup-memory";
986 power-domains = <&rpmhpd RPMHPD_CX>;
987 required-opps = <&rpmhpd_opp_low_svs>;
990 dma-names = "tx",
996 compatible = "qcom,geni-spi";
999 clock-names = "se";
1000 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1001 pinctrl-names = "default";
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1009 interconnect-names = "qup-core",
1010 "qup-config";
1011 power-domains = <&rpmhpd RPMHPD_CX>;
1012 operating-points-v2 = <&qup_opp_table>;
1015 dma-names = "tx",
1021 compatible = "qcom,geni-uart";
1024 clock-names = "se";
1025 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>,
1027 pinctrl-names = "default";
1033 interconnect-names = "qup-core",
1034 "qup-config";
1035 power-domains = <&rpmhpd RPMHPD_CX>;
1036 operating-points-v2 = <&qup_opp_table>;
1043 compatible = "qcom,qcs615-config-noc";
1044 #interconnect-cells = <2>;
1045 qcom,bcm-voters = <&apps_bcm_voter>;
1050 compatible = "qcom,qcs615-system-noc";
1051 #interconnect-cells = <2>;
1052 qcom,bcm-voters = <&apps_bcm_voter>;
1057 compatible = "qcom,qcs615-aggre1-noc";
1058 #interconnect-cells = <2>;
1059 qcom,bcm-voters = <&apps_bcm_voter>;
1064 compatible = "qcom,qcs615-mmss-noc";
1065 #interconnect-cells = <2>;
1066 qcom,bcm-voters = <&apps_bcm_voter>;
1070 compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1073 reg-names = "std",
1086 clock-names = "core_clk",
1096 reset-names = "rst";
1098 operating-points-v2 = <&ufs_opp_table>;
1103 interconnect-names = "ufs-ddr",
1104 "cpu-ufs";
1106 power-domains = <&gcc UFS_PHY_GDSC>;
1109 dma-coherent;
1111 lanes-per-direction = <1>;
1114 phy-names = "ufsphy";
1116 #reset-cells = <1>;
1120 ufs_opp_table: opp-table {
1121 compatible = "operating-points-v2";
1123 opp-50000000 {
1124 opp-hz = /bits/ 64 <50000000>,
1132 required-opps = <&rpmhpd_opp_low_svs>;
1135 opp-100000000 {
1136 opp-hz = /bits/ 64 <100000000>,
1144 required-opps = <&rpmhpd_opp_svs>;
1147 opp-200000000 {
1148 opp-hz = /bits/ 64 <200000000>,
1156 required-opps = <&rpmhpd_opp_nom>;
1162 compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy";
1167 clock-names = "ref",
1171 power-domains = <&gcc UFS_PHY_GDSC>;
1174 reset-names = "ufsphy";
1176 #clock-cells = <1>;
1177 #phy-cells = <0>;
1182 cryptobam: dma-controller@1dc4000 {
1183 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
1186 #dma-cells = <1>;
1188 qcom,controlled-remotely;
1189 num-channels = <16>;
1190 qcom,num-ees = <4>;
1195 compatible = "qcom,qcs615-qce", "qcom,sm8150-qce", "qcom,qce";
1198 dma-names = "rx", "tx";
1202 interconnect-names = "memory";
1206 compatible = "qcom,tcsr-mutex";
1208 #hwlock-cells = <1>;
1212 compatible = "qcom,qcs615-tcsr", "syscon";
1217 compatible = "qcom,qcs615-tlmm";
1221 reg-names = "east",
1225 gpio-ranges = <&tlmm 0 0 124>;
1226 gpio-controller;
1227 #gpio-cells = <2>;
1228 interrupt-controller;
1229 #interrupt-cells = <2>;
1230 wakeup-parent = <&pdc>;
1232 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
1238 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
1243 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
1248 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
1253 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1258 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1263 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
1268 qup_spi2_data_clk: qup-spi2-data-clk-state {
1273 qup_spi2_cs: qup-spi2-cs-state {
1278 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
1283 qup_spi4_data_clk: qup-spi4-data-clk-state {
1288 qup_spi4_cs: qup-spi4-cs-state {
1293 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
1298 qup_spi6_data_clk: qup-spi6-data-clk-state {
1303 qup_spi6_cs: qup-spi6-cs-state {
1308 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1313 qup_spi7_data_clk: qup-spi7-data-clk-state {
1318 qup_spi7_cs: qup-spi7-cs-state {
1323 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
1328 qup_uart0_tx: qup-uart0-tx-state {
1333 qup_uart0_rx: qup-uart0-rx-state {
1338 qup_uart2_cts: qup-uart2-cts-state {
1343 qup_uart2_rts: qup-uart2-rts-state {
1348 qup_uart2_tx: qup-uart2-tx-state {
1353 qup_uart2_rx: qup-uart2-rx-state {
1358 qup_uart4_cts: qup-uart4-cts-state {
1363 qup_uart4_rts: qup-uart4-rts-state {
1368 qup_uart4_tx: qup-uart4-tx-state {
1373 qup_uart4_rx: qup-uart4-rx-state {
1378 qup_uart6_cts: qup-uart6-cts-state {
1383 qup_uart6_rts: qup-uart6-rts-state {
1388 qup_uart6_tx: qup-uart6-tx-state {
1393 qup_uart6_rx: qup-uart6-rx-state {
1398 qup_uart7_cts: qup-uart7-cts-state {
1403 qup_uart7_rts: qup-uart7-rts-state {
1408 qup_uart7_tx: qup-uart7-tx-state {
1413 qup_uart7_rx: qup-uart7-rx-state {
1418 sdc1_state_on: sdc1-on-state {
1419 clk-pins {
1421 bias-disable;
1422 drive-strength = <16>;
1425 cmd-pins {
1427 bias-pull-up;
1428 drive-strength = <10>;
1431 data-pins {
1433 bias-pull-up;
1434 drive-strength = <10>;
1437 rclk-pins {
1439 bias-pull-down;
1443 sdc1_state_off: sdc1-off-state {
1444 clk-pins {
1446 bias-disable;
1447 drive-strength = <2>;
1450 cmd-pins {
1452 bias-pull-up;
1453 drive-strength = <2>;
1456 data-pins {
1458 bias-pull-up;
1459 drive-strength = <2>;
1462 rclk-pins {
1464 bias-pull-down;
1468 sdc2_state_on: sdc2-on-state {
1469 clk-pins {
1471 bias-disable;
1472 drive-strength = <16>;
1475 cmd-pins {
1477 bias-pull-up;
1478 drive-strength = <10>;
1481 data-pins {
1483 bias-pull-up;
1484 drive-strength = <10>;
1488 sdc2_state_off: sdc2-off-state {
1489 clk-pins {
1491 bias-disable;
1492 drive-strength = <2>;
1495 cmd-pins {
1497 bias-pull-up;
1498 drive-strength = <2>;
1501 data-pins {
1503 bias-pull-up;
1504 drive-strength = <2>;
1510 compatible = "arm,coresight-stm", "arm,primecell";
1513 reg-names = "stm-base",
1514 "stm-stimulus-base";
1517 clock-names = "apb_pclk";
1519 out-ports {
1522 remote-endpoint = <&funnel_in0_in7>;
1529 compatible = "qcom,coresight-tpda", "arm,primecell";
1533 clock-names = "apb_pclk";
1535 in-ports {
1536 #address-cells = <1>;
1537 #size-cells = <0>;
1543 remote-endpoint = <&tpdm_center_out>;
1551 remote-endpoint = <&funnel_monaq_out>;
1559 remote-endpoint = <&funnel_ddr_0_out>;
1567 remote-endpoint = <&funnel_turing_out>;
1575 remote-endpoint = <&tpdm_vsense_out>;
1583 remote-endpoint = <&tpdm_dcc_out>;
1591 remote-endpoint = <&tpdm_prng_out>;
1599 remote-endpoint = <&tpdm_qm_out>;
1607 remote-endpoint = <&tpdm_west_out>;
1615 remote-endpoint = <&tpdm_pimem_out>;
1620 out-ports {
1623 remote-endpoint = <&funnel_qatb_in>;
1630 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1634 clock-names = "apb_pclk";
1636 in-ports {
1639 remote-endpoint = <&tpda_qdss_out>;
1644 out-ports {
1647 remote-endpoint = <&funnel_in0_in6>;
1654 compatible = "arm,coresight-cti", "arm,primecell";
1658 clock-names = "apb_pclk";
1662 compatible = "arm,coresight-cti", "arm,primecell";
1666 clock-names = "apb_pclk";
1670 compatible = "arm,coresight-cti", "arm,primecell";
1674 clock-names = "apb_pclk";
1678 compatible = "arm,coresight-cti", "arm,primecell";
1682 clock-names = "apb_pclk";
1686 compatible = "arm,coresight-cti", "arm,primecell";
1690 clock-names = "apb_pclk";
1694 compatible = "arm,coresight-cti", "arm,primecell";
1698 clock-names = "apb_pclk";
1702 compatible = "arm,coresight-cti", "arm,primecell";
1706 clock-names = "apb_pclk";
1710 compatible = "arm,coresight-cti", "arm,primecell";
1714 clock-names = "apb_pclk";
1718 compatible = "arm,coresight-cti", "arm,primecell";
1722 clock-names = "apb_pclk";
1726 compatible = "arm,coresight-cti", "arm,primecell";
1730 clock-names = "apb_pclk";
1734 compatible = "arm,coresight-cti", "arm,primecell";
1738 clock-names = "apb_pclk";
1742 compatible = "arm,coresight-cti", "arm,primecell";
1746 clock-names = "apb_pclk";
1750 compatible = "arm,coresight-cti", "arm,primecell";
1754 clock-names = "apb_pclk";
1758 compatible = "arm,coresight-cti", "arm,primecell";
1762 clock-names = "apb_pclk";
1766 compatible = "arm,coresight-cti", "arm,primecell";
1770 clock-names = "apb_pclk";
1774 compatible = "arm,coresight-cti", "arm,primecell";
1778 clock-names = "apb_pclk";
1782 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1786 clock-names = "apb_pclk";
1788 in-ports {
1789 #address-cells = <1>;
1790 #size-cells = <0>;
1796 remote-endpoint = <&funnel_qatb_out>;
1804 remote-endpoint = <&stm_out>;
1809 out-ports {
1812 remote-endpoint = <&funnel_merg_in0>;
1819 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1823 clock-names = "apb_pclk";
1825 in-ports {
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1833 remote-endpoint = <&replicator_swao_out0>;
1841 remote-endpoint = <&tpdm_wcss_out>;
1849 remote-endpoint = <&funnel_apss_merg_out>;
1854 out-ports {
1857 remote-endpoint = <&funnel_merg_in1>;
1864 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1868 clock-names = "apb_pclk";
1870 in-ports {
1871 #address-cells = <1>;
1872 #size-cells = <0>;
1878 remote-endpoint = <&funnel_in0_out>;
1886 remote-endpoint = <&funnel_in1_out>;
1891 out-ports {
1894 remote-endpoint = <&tmc_etf_in>;
1901 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1905 clock-names = "apb_pclk";
1907 in-ports {
1910 remote-endpoint = <&tmc_etf_out>;
1915 out-ports {
1916 #address-cells = <1>;
1917 #size-cells = <0>;
1923 remote-endpoint = <&replicator1_in>;
1929 tmc@6047000 {
1930 compatible = "arm,coresight-tmc", "arm,primecell";
1934 clock-names = "apb_pclk";
1936 in-ports {
1939 remote-endpoint = <&funnel_merg_out>;
1944 out-ports {
1947 remote-endpoint = <&replicator0_in>;
1954 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1958 clock-names = "apb_pclk";
1961 in-ports {
1964 remote-endpoint = <&replicator0_out1>;
1969 out-ports {
1972 remote-endpoint = <&funnel_swao_in6>;
1979 compatible = "arm,coresight-cti", "arm,primecell";
1983 clock-names = "apb_pclk";
1987 compatible = "qcom,coresight-tpdm", "arm,primecell";
1991 clock-names = "apb_pclk";
1993 qcom,cmb-element-bits = <64>;
1994 qcom,cmb-msrs-num = <32>;
1997 out-ports {
2000 remote-endpoint = <&tpda_qdss_in7>;
2007 compatible = "qcom,coresight-tpdm", "arm,primecell";
2011 clock-names = "apb_pclk";
2013 qcom,cmb-element-bits = <32>;
2014 qcom,cmb-msrs-num = <32>;
2016 out-ports {
2019 remote-endpoint = <&tpda_qdss_in9>;
2026 compatible = "qcom,coresight-tpdm", "arm,primecell";
2030 clock-names = "apb_pclk";
2032 qcom,cmb-element-bits = <64>;
2033 qcom,cmb-msrs-num = <32>;
2034 qcom,dsb-element-bits = <32>;
2035 qcom,dsb-msrs-num = <32>;
2037 out-ports {
2040 remote-endpoint = <&tpda_qdss_in13>;
2047 compatible = "qcom,coresight-tpdm", "arm,primecell";
2051 clock-names = "apb_pclk";
2053 qcom,dsb-element-bits = <32>;
2054 qcom,dsb-msrs-num = <32>;
2056 out-ports {
2059 remote-endpoint = <&funnel_turing_in>;
2066 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2070 clock-names = "apb_pclk";
2072 in-ports {
2075 remote-endpoint = <&tpdm_turing_out>;
2080 out-ports {
2083 remote-endpoint = <&tpda_qdss_in6>;
2090 compatible = "arm,coresight-cti", "arm,primecell";
2094 clock-names = "apb_pclk";
2098 compatible = "qcom,coresight-tpdm", "arm,primecell";
2102 clock-names = "apb_pclk";
2104 qcom,cmb-element-bits = <32>;
2105 qcom,cmb-msrs-num = <32>;
2108 out-ports {
2111 remote-endpoint = <&tpda_qdss_in8>;
2118 compatible = "qcom,coresight-tpdm", "arm,primecell";
2122 clock-names = "apb_pclk";
2124 qcom,cmb-element-bits = <32>;
2125 qcom,cmb-msrs-num = <32>;
2126 qcom,dsb-element-bits = <32>;
2127 qcom,dsb-msrs-num = <32>;
2130 out-ports {
2133 remote-endpoint = <&funnel_in1_in4>;
2140 compatible = "qcom,coresight-tpdm", "arm,primecell";
2144 clock-names = "apb_pclk";
2146 qcom,dsb-element-bits = <32>;
2147 qcom,dsb-msrs-num = <32>;
2149 out-ports {
2152 remote-endpoint = <&funnel_monaq_in>;
2159 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2163 clock-names = "apb_pclk";
2165 in-ports {
2168 remote-endpoint = <&tpdm_monaq_out>;
2173 out-ports {
2176 remote-endpoint = <&tpda_qdss_in4>;
2183 compatible = "qcom,coresight-tpdm", "arm,primecell";
2187 clock-names = "apb_pclk";
2189 qcom,dsb-element-bits = <32>;
2190 qcom,dsb-msrs-num = <32>;
2193 out-ports {
2196 remote-endpoint = <&tpda_qdss_in11>;
2203 compatible = "qcom,coresight-tpdm", "arm,primecell";
2207 clock-names = "apb_pclk";
2209 qcom,dsb-element-bits = <32>;
2210 qcom,dsb-msrs-num = <32>;
2213 out-ports {
2216 remote-endpoint = <&funnel_ddr_0_in>;
2223 compatible = "arm,coresight-cti", "arm,primecell";
2227 clock-names = "apb_pclk";
2231 compatible = "arm,coresight-cti", "arm,primecell";
2235 clock-names = "apb_pclk";
2239 compatible = "arm,coresight-cti", "arm,primecell";
2243 clock-names = "apb_pclk";
2247 compatible = "arm,coresight-cti", "arm,primecell";
2251 clock-names = "apb_pclk";
2255 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2259 clock-names = "apb_pclk";
2261 in-ports {
2264 remote-endpoint = <&tpdm_ddr_out>;
2269 out-ports {
2272 remote-endpoint = <&tpda_qdss_in5>;
2279 compatible = "qcom,coresight-tpda", "arm,primecell";
2283 clock-names = "apb_pclk";
2285 in-ports {
2286 #address-cells = <1>;
2287 #size-cells = <0>;
2293 remote-endpoint = <&tpdm_swao0_out>;
2301 remote-endpoint = <&tpdm_swao1_out>;
2307 out-ports {
2310 remote-endpoint = <&funnel_swao_in7>;
2317 compatible = "qcom,coresight-tpdm", "arm,primecell";
2321 clock-names = "apb_pclk";
2323 qcom,cmb-element-bits = <64>;
2324 qcom,cmb-msrs-num = <32>;
2327 out-ports {
2330 remote-endpoint = <&tpda_swao_in0>;
2337 compatible = "qcom,coresight-tpdm", "arm,primecell";
2341 clock-names = "apb_pclk";
2343 qcom,dsb-element-bits = <32>;
2344 qcom,dsb-msrs-num = <32>;
2347 out-ports {
2350 remote-endpoint = <&tpda_swao_in1>;
2357 compatible = "arm,coresight-cti", "arm,primecell";
2361 clock-names = "apb_pclk";
2365 compatible = "arm,coresight-cti", "arm,primecell";
2369 clock-names = "apb_pclk";
2373 compatible = "arm,coresight-cti", "arm,primecell";
2377 clock-names = "apb_pclk";
2381 compatible = "arm,coresight-cti", "arm,primecell";
2385 clock-names = "apb_pclk";
2389 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2393 clock-names = "apb_pclk";
2395 in-ports {
2396 #address-cells = <1>;
2397 #size-cells = <0>;
2403 remote-endpoint = <&replicator1_out>;
2411 remote-endpoint = <&tpda_swao_out>;
2416 out-ports {
2419 remote-endpoint = <&tmc_etf_swao_in>;
2425 tmc@6b09000 {
2426 compatible = "arm,coresight-tmc", "arm,primecell";
2430 clock-names = "apb_pclk";
2432 in-ports {
2435 remote-endpoint = <&funnel_swao_out>;
2440 out-ports {
2443 remote-endpoint = <&replicator_swao_in>;
2450 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2454 clock-names = "apb_pclk";
2456 in-ports {
2459 remote-endpoint = <&tmc_etf_swao_out>;
2464 out-ports {
2465 #address-cells = <1>;
2466 #size-cells = <0>;
2472 remote-endpoint = <&funnel_in1_in3>;
2480 remote-endpoint = <&eud_in>;
2487 compatible = "arm,coresight-cti", "arm,primecell";
2491 clock-names = "apb_pclk";
2495 compatible = "qcom,coresight-tpdm", "arm,primecell";
2499 clock-names = "apb_pclk";
2501 qcom,dsb-element-bits = <32>;
2502 qcom,dsb-msrs-num = <32>;
2504 out-ports {
2507 remote-endpoint = <&tpda_qdss_in12>;
2514 compatible = "arm,coresight-cti", "arm,primecell";
2518 clock-names = "apb_pclk";
2525 compatible = "arm,coresight-cti", "arm,primecell";
2529 clock-names = "apb_pclk";
2534 compatible = "qcom,coresight-tpdm", "arm,primecell";
2538 clock-names = "apb_pclk";
2540 qcom,dsb-element-bits = <32>;
2541 qcom,dsb-msrs-num = <32>;
2543 out-ports {
2546 remote-endpoint = <&tpda_qdss_in0>;
2553 compatible = "arm,coresight-cti", "arm,primecell";
2557 clock-names = "apb_pclk";
2561 compatible = "arm,coresight-cti", "arm,primecell";
2565 clock-names = "apb_pclk";
2569 compatible = "arm,coresight-cti", "arm,primecell";
2573 clock-names = "apb_pclk";
2582 clock-names = "apb_pclk";
2584 arm,coresight-loses-context-with-cpu;
2585 qcom,skip-power-up;
2587 out-ports {
2590 remote-endpoint = <&funnel_apss_in0>;
2597 compatible = "arm,coresight-cti", "arm,primecell";
2601 clock-names = "apb_pclk";
2610 clock-names = "apb_pclk";
2612 arm,coresight-loses-context-with-cpu;
2613 qcom,skip-power-up;
2615 out-ports {
2618 remote-endpoint = <&funnel_apss_in1>;
2625 compatible = "arm,coresight-cti", "arm,primecell";
2629 clock-names = "apb_pclk";
2638 clock-names = "apb_pclk";
2640 arm,coresight-loses-context-with-cpu;
2641 qcom,skip-power-up;
2643 out-ports {
2646 remote-endpoint = <&funnel_apss_in2>;
2653 compatible = "arm,coresight-cti", "arm,primecell";
2657 clock-names = "apb_pclk";
2666 clock-names = "apb_pclk";
2668 arm,coresight-loses-context-with-cpu;
2669 qcom,skip-power-up;
2671 out-ports {
2674 remote-endpoint = <&funnel_apss_in3>;
2681 compatible = "arm,coresight-cti", "arm,primecell";
2685 clock-names = "apb_pclk";
2694 clock-names = "apb_pclk";
2696 arm,coresight-loses-context-with-cpu;
2697 qcom,skip-power-up;
2699 out-ports {
2702 remote-endpoint = <&funnel_apss_in4>;
2709 compatible = "arm,coresight-cti", "arm,primecell";
2713 clock-names = "apb_pclk";
2722 clock-names = "apb_pclk";
2724 arm,coresight-loses-context-with-cpu;
2725 qcom,skip-power-up;
2727 out-ports {
2730 remote-endpoint = <&funnel_apss_in5>;
2737 compatible = "arm,coresight-cti", "arm,primecell";
2741 clock-names = "apb_pclk";
2750 clock-names = "apb_pclk";
2752 arm,coresight-loses-context-with-cpu;
2753 qcom,skip-power-up;
2755 out-ports {
2758 remote-endpoint = <&funnel_apss_in6>;
2765 compatible = "arm,coresight-cti", "arm,primecell";
2769 clock-names = "apb_pclk";
2778 clock-names = "apb_pclk";
2780 arm,coresight-loses-context-with-cpu;
2781 qcom,skip-power-up;
2783 out-ports {
2786 remote-endpoint = <&funnel_apss_in7>;
2793 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2797 clock-names = "apb_pclk";
2799 in-ports {
2800 #address-cells = <1>;
2801 #size-cells = <0>;
2807 remote-endpoint = <&etm0_out>;
2815 remote-endpoint = <&etm1_out>;
2823 remote-endpoint = <&etm2_out>;
2831 remote-endpoint = <&etm3_out>;
2839 remote-endpoint = <&etm4_out>;
2847 remote-endpoint = <&etm5_out>;
2855 remote-endpoint = <&etm6_out>;
2863 remote-endpoint = <&etm7_out>;
2868 out-ports {
2871 remote-endpoint = <&funnel_apss_merg_in0>;
2878 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2882 clock-names = "apb_pclk";
2884 in-ports {
2885 #address-cells = <1>;
2886 #size-cells = <0>;
2892 remote-endpoint = <&funnel_apss_out>;
2900 remote-endpoint = <&tpda_olc_out>;
2908 remote-endpoint = <&tpda_llm_silver_out>;
2916 remote-endpoint = <&tpda_llm_gold_out>;
2924 remote-endpoint = <&tpda_apss_out>;
2929 out-ports {
2932 remote-endpoint = <&funnel_in1_in7>;
2939 compatible = "qcom,coresight-tpdm", "arm,primecell";
2943 clock-names = "apb_pclk";
2945 qcom,cmb-element-bits = <64>;
2946 qcom,cmb-msrs-num = <32>;
2948 out-ports {
2951 remote-endpoint = <&tpda_olc_in>;
2958 compatible = "qcom,coresight-tpda", "arm,primecell";
2962 clock-names = "apb_pclk";
2964 in-ports {
2967 remote-endpoint = <&tpdm_olc_out>;
2972 out-ports {
2975 remote-endpoint = <&funnel_apss_merg_in2>;
2982 compatible = "qcom,coresight-tpdm", "arm,primecell";
2986 clock-names = "apb_pclk";
2988 qcom,dsb-element-bits = <32>;
2989 qcom,dsb-msrs-num = <32>;
2991 out-ports {
2994 remote-endpoint = <&tpda_apss_in>;
3001 compatible = "qcom,coresight-tpda", "arm,primecell";
3005 clock-names = "apb_pclk";
3007 in-ports {
3010 remote-endpoint = <&tpdm_apss_out>;
3015 out-ports {
3018 remote-endpoint = <&funnel_apss_merg_in5>;
3025 compatible = "qcom,coresight-tpdm", "arm,primecell";
3029 clock-names = "apb_pclk";
3031 qcom,cmb-element-bits = <32>;
3032 qcom,cmb-msrs-num = <32>;
3034 out-ports {
3037 remote-endpoint = <&tpda_llm_silver_in>;
3044 compatible = "qcom,coresight-tpdm", "arm,primecell";
3048 clock-names = "apb_pclk";
3050 qcom,cmb-element-bits = <32>;
3051 qcom,cmb-msrs-num = <32>;
3053 out-ports {
3056 remote-endpoint = <&tpda_llm_gold_in>;
3063 compatible = "qcom,coresight-tpda", "arm,primecell";
3067 clock-names = "apb_pclk";
3069 in-ports {
3072 remote-endpoint = <&tpdm_llm_silver_out>;
3077 out-ports {
3080 remote-endpoint = <&funnel_apss_merg_in3>;
3087 compatible = "qcom,coresight-tpda", "arm,primecell";
3091 clock-names = "apb_pclk";
3093 in-ports {
3096 remote-endpoint = <&tpdm_llm_gold_out>;
3101 out-ports {
3104 remote-endpoint = <&funnel_apss_merg_in4>;
3111 compatible = "arm,coresight-cti", "arm,primecell";
3115 clock-names = "apb_pclk";
3119 compatible = "arm,coresight-cti", "arm,primecell";
3123 clock-names = "apb_pclk";
3127 compatible = "arm,coresight-cti", "arm,primecell";
3131 clock-names = "apb_pclk";
3135 compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas";
3138 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
3143 interrupt-names = "wdog",
3147 "stop-ack";
3150 clock-names = "xo";
3152 power-domains = <&rpmhpd RPMHPD_CX>;
3153 power-domain-names = "cx";
3155 memory-region = <&rproc_cdsp_mem>;
3159 qcom,smem-states = <&cdsp_smp2p_out 0>;
3160 qcom,smem-state-names = "stop";
3164 glink-edge {
3168 qcom,remote-pid = <5>;
3173 compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon";
3179 operating-points-v2 = <&cpu_bwmon_opp_table>;
3181 cpu_bwmon_opp_table: opp-table {
3182 compatible = "operating-points-v2";
3184 opp-0 {
3185 opp-peak-kBps = <12896000>;
3188 opp-1 {
3189 opp-peak-kBps = <14928000>;
3195 compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3201 operating-points-v2 = <&llcc_bwmon_opp_table>;
3203 llcc_bwmon_opp_table: opp-table {
3204 compatible = "operating-points-v2";
3206 opp-0 {
3207 opp-peak-kBps = <800000>;
3210 opp-1 {
3211 opp-peak-kBps = <1200000>;
3214 opp-2 {
3215 opp-peak-kBps = <1804800>;
3218 opp-3 {
3219 opp-peak-kBps = <2188800>;
3222 opp-4 {
3223 opp-peak-kBps = <2726400>;
3226 opp-5 {
3227 opp-peak-kBps = <3072000>;
3230 opp-6 {
3231 opp-peak-kBps = <4070400>;
3234 opp-7 {
3235 opp-peak-kBps = <5414400>;
3238 opp-8 {
3239 opp-peak-kBps = <6220800>;
3245 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5";
3247 reg-names = "hc";
3251 interrupt-names = "hc_irq",
3257 clock-names = "iface",
3261 power-domains = <&rpmhpd RPMHPD_CX>;
3262 operating-points-v2 = <&sdhc2_opp_table>;
3269 interconnect-names = "sdhc-ddr",
3270 "cpu-sdhc";
3272 qcom,dll-config = <0x0007642c>;
3273 qcom,ddr-config = <0x80040868>;
3274 dma-coherent;
3278 sdhc2_opp_table: opp-table {
3279 compatible = "operating-points-v2";
3281 opp-50000000 {
3282 opp-hz = /bits/ 64 <50000000>;
3283 required-opps = <&rpmhpd_opp_low_svs>;
3286 opp-100000000 {
3287 opp-hz = /bits/ 64 <100000000>;
3288 required-opps = <&rpmhpd_opp_svs>;
3291 opp-202000000 {
3292 opp-hz = /bits/ 64 <202000000>;
3293 required-opps = <&rpmhpd_opp_nom>;
3300 compatible = "qcom,qcs615-dc-noc";
3301 #interconnect-cells = <2>;
3302 qcom,bcm-voters = <&apps_bcm_voter>;
3305 llcc: system-cache-controller@9200000 {
3306 compatible = "qcom,qcs615-llcc";
3309 reg-names = "llcc0_base",
3315 compatible = "qcom,qcs615-gem-noc";
3316 #interconnect-cells = <2>;
3317 qcom,bcm-voters = <&apps_bcm_voter>;
3320 pdc: interrupt-controller@b220000 {
3321 compatible = "qcom,qcs615-pdc", "qcom,pdc";
3324 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3325 interrupt-parent = <&intc>;
3326 #interrupt-cells = <2>;
3327 interrupt-controller;
3330 aoss_qmp: power-management@c300000 {
3331 compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp";
3336 #clock-cells = <0>;
3340 compatible = "qcom,rpmh-stats";
3345 compatible = "qcom,qcs615-imem", "syscon", "simple-mfd";
3349 #address-cells = <1>;
3350 #size-cells = <1>;
3352 pil-reloc@2a94c {
3353 compatible = "qcom,pil-reloc-info";
3359 compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500";
3361 #iommu-cells = <2>;
3362 #global-interrupts = <1>;
3363 dma-coherent;
3433 compatible = "qcom,spmi-pmic-arb";
3439 reg-names = "core",
3444 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3445 interrupt-names = "periph_irq";
3446 interrupt-controller;
3447 #interrupt-cells = <4>;
3448 #address-cells = <2>;
3449 #size-cells = <0>;
3454 intc: interrupt-controller@17a00000 {
3455 compatible = "arm,gic-v3";
3459 #interrupt-cells = <3>;
3460 interrupt-controller;
3461 #redistributor-regions = <1>;
3462 redistributor-stride = <0x0 0x20000>;
3466 compatible = "qcom,qcs615-apss-shared",
3467 "qcom,sdm845-apss-shared";
3469 #mbox-cells = <1>;
3473 compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt";
3479 compatible = "arm,armv7-timer-mem";
3482 #address-cells = <1>;
3483 #size-cells = <1>;
3488 frame-number = <0>;
3495 frame-number = <1>;
3502 frame-number = <2>;
3509 frame-number = <3>;
3516 frame-number = <4>;
3523 frame-number = <5>;
3530 frame-number = <6>;
3537 compatible = "qcom,rpmh-rsc";
3541 reg-names = "drv-0",
3542 "drv-1",
3543 "drv-2";
3549 qcom,drv-id = <2>;
3550 qcom,tcs-offset = <0xd00>;
3551 qcom,tcs-config = <ACTIVE_TCS 2>,
3557 power-domains = <&cluster_pd>;
3559 apps_bcm_voter: bcm-voter {
3560 compatible = "qcom,bcm-voter";
3563 rpmhcc: clock-controller {
3564 compatible = "qcom,qcs615-rpmh-clk";
3565 clock-names = "xo";
3567 #clock-cells = <1>;
3570 rpmhpd: power-controller {
3571 compatible = "qcom,qcs615-rpmhpd";
3572 #power-domain-cells = <1>;
3573 operating-points-v2 = <&rpmhpd_opp_table>;
3575 rpmhpd_opp_table: opp-table {
3576 compatible = "operating-points-v2";
3578 rpmhpd_opp_ret: opp-0 {
3579 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3582 rpmhpd_opp_min_svs: opp-1 {
3583 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3586 rpmhpd_opp_low_svs: opp-2 {
3587 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3590 rpmhpd_opp_svs: opp-3 {
3591 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3594 rpmhpd_opp_svs_l1: opp-4 {
3595 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3598 rpmhpd_opp_nom: opp-5 {
3599 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3602 rpmhpd_opp_nom_l1: opp-6 {
3603 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3606 rpmhpd_opp_nom_l2: opp-7 {
3607 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3610 rpmhpd_opp_turbo: opp-8 {
3611 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3614 rpmhpd_opp_turbo_l1: opp-9 {
3615 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3622 compatible = "qcom,qcs615-qusb2-phy";
3626 clock-names = "cfg_ahb", "ref";
3629 nvmem-cells = <&qusb2_hstx_trim>;
3631 #phy-cells = <0>;
3637 compatible = "qcom,qcs615-qusb2-phy";
3642 clock-names = "cfg_ahb",
3647 #phy-cells = <0>;
3653 compatible = "qcom,qcs615-qmp-usb3-phy";
3660 clock-names = "aux",
3667 reset-names = "phy", "phy_phy";
3669 qcom,tcsr-reg = <&tcsr 0xb244>;
3671 clock-output-names = "usb3_phy_pipe_clk_src";
3672 #clock-cells = <0>;
3674 #phy-cells = <0>;
3680 compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
3689 clock-names = "cfg_noc",
3696 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3698 assigned-clock-rates = <19200000>, <200000000>;
3700 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
3705 interrupt-names = "pwr_event",
3711 power-domains = <&gcc USB30_PRIM_GDSC>;
3712 required-opps = <&rpmhpd_opp_nom>;
3716 #address-cells = <2>;
3717 #size-cells = <2>;
3730 phy-names = "usb2-phy", "usb3-phy";
3732 snps,dis-u1-entry-quirk;
3733 snps,dis-u2-entry-quirk;
3737 snps,has-lpm-erratum;
3738 snps,hird-threshold = /bits/ 8 <0x10>;
3744 compatible = "qcom,qcs615-dwc3", "qcom,dwc3";
3753 clock-names = "cfg_noc",
3760 assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>,
3762 assigned-clock-rates = <19200000>, <200000000>;
3764 interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>,
3768 interrupt-names = "pwr_event",
3773 power-domains = <&gcc USB20_SEC_GDSC>;
3774 required-opps = <&rpmhpd_opp_nom>;
3778 qcom,select-utmi-as-pipe-clk;
3780 #address-cells = <2>;
3781 #size-cells = <2>;
3794 phy-names = "usb2-phy";
3799 snps,has-lpm-erratum;
3800 snps,hird-threshold = /bits/ 8 <0x10>;
3802 maximum-speed = "high-speed";
3807 compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas";
3810 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3815 interrupt-names = "wdog",
3819 "stop-ack";
3822 clock-names = "xo";
3824 power-domains = <&rpmhpd RPMHPD_CX>;
3825 power-domain-names = "cx";
3827 memory-region = <&rproc_adsp_mem>;
3831 qcom,smem-states = <&adsp_smp2p_out 0>;
3832 qcom,smem-state-names = "stop";
3836 glink_edge: glink-edge {
3840 qcom,remote-pid = <2>;
3846 compatible = "arm,armv8-timer";